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| author | Xi Ruoyao <xry111@xry111.site> | 2023-11-17 20:44:17 +0800 |
|---|---|---|
| committer | Xi Ruoyao <xry111@xry111.site> | 2023-11-19 01:11:09 +0800 |
| commit | 56752a6bbfb3d3501d0899b23020c3e2eb58882c (patch) | |
| tree | 1fb8f488fca33ce25477d45c0246edd687a4a23b /gcc | |
| parent | 20a3c74c347429c109bc7002285b735be83f6a0b (diff) | |
| download | gcc-56752a6bbfb3d3501d0899b23020c3e2eb58882c.zip gcc-56752a6bbfb3d3501d0899b23020c3e2eb58882c.tar.gz gcc-56752a6bbfb3d3501d0899b23020c3e2eb58882c.tar.bz2 | |
LoongArch: Fix internal error running "gcc -march=native" on LA664
On LA664, the PRID preset is ISA_BASE_LA64V110 but the base architecture
is guessed ISA_BASE_LA64V100. This causes a warning to be outputed:
cc1: warning: base architecture 'la64' differs from PRID preset '?'
But we've not set the "?" above in loongarch_isa_base_strings, thus it's
a nullptr and then an ICE is triggered.
Add ISA_BASE_LA64V110 to genopts and initialize
loongarch_isa_base_strings[ISA_BASE_LA64V110] correctly to fix the ICE.
The warning itself will be fixed later.
gcc/ChangeLog:
* config/loongarch/genopts/loongarch-strings:
(STR_ISA_BASE_LA64V110): Add.
* config/loongarch/genopts/loongarch.opt.in:
(ISA_BASE_LA64V110): Add.
* config/loongarch/loongarch-def.c
(loongarch_isa_base_strings): Initialize [ISA_BASE_LA64V110]
to STR_ISA_BASE_LA64V110.
* config/loongarch/loongarch.opt: Regenerate.
* config/loongarch/loongarch-str.h: Regenerate.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/loongarch/genopts/loongarch-strings | 1 | ||||
| -rw-r--r-- | gcc/config/loongarch/genopts/loongarch.opt.in | 3 | ||||
| -rw-r--r-- | gcc/config/loongarch/loongarch-def.c | 1 | ||||
| -rw-r--r-- | gcc/config/loongarch/loongarch-str.h | 1 | ||||
| -rw-r--r-- | gcc/config/loongarch/loongarch.opt | 3 |
5 files changed, 9 insertions, 0 deletions
diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings index 7bc4824..b2070c8 100644 --- a/gcc/config/loongarch/genopts/loongarch-strings +++ b/gcc/config/loongarch/genopts/loongarch-strings @@ -30,6 +30,7 @@ STR_CPU_LA664 la664 # Base architecture STR_ISA_BASE_LA64V100 la64 +STR_ISA_BASE_LA64V110 la64v1.1 # -mfpu OPTSTR_ISA_EXT_FPU fpu diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in index 00b4733..b274b3f 100644 --- a/gcc/config/loongarch/genopts/loongarch.opt.in +++ b/gcc/config/loongarch/genopts/loongarch.opt.in @@ -32,6 +32,9 @@ Basic ISAs of LoongArch: EnumValue Enum(isa_base) String(@@STR_ISA_BASE_LA64V100@@) Value(ISA_BASE_LA64V100) +EnumValue +Enum(isa_base) String(@@STR_ISA_BASE_LA64V110@@) Value(ISA_BASE_LA64V110) + ;; ISA extensions / adjustments Enum Name(isa_ext_fpu) Type(int) diff --git a/gcc/config/loongarch/loongarch-def.c b/gcc/config/loongarch/loongarch-def.c index 0676291..f22d488 100644 --- a/gcc/config/loongarch/loongarch-def.c +++ b/gcc/config/loongarch/loongarch-def.c @@ -165,6 +165,7 @@ loongarch_cpu_multipass_dfa_lookahead[N_TUNE_TYPES] = { const char* loongarch_isa_base_strings[N_ISA_BASE_TYPES] = { [ISA_BASE_LA64V100] = STR_ISA_BASE_LA64V100, + [ISA_BASE_LA64V110] = STR_ISA_BASE_LA64V110, }; const char* diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h index fc4f41b..114dbc6 100644 --- a/gcc/config/loongarch/loongarch-str.h +++ b/gcc/config/loongarch/loongarch-str.h @@ -33,6 +33,7 @@ along with GCC; see the file COPYING3. If not see #define STR_CPU_LA664 "la664" #define STR_ISA_BASE_LA64V100 "la64" +#define STR_ISA_BASE_LA64V110 "la64v1.1" #define OPTSTR_ISA_EXT_FPU "fpu" #define STR_NONE "none" diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt index 7f129e5..350ca30 100644 --- a/gcc/config/loongarch/loongarch.opt +++ b/gcc/config/loongarch/loongarch.opt @@ -39,6 +39,9 @@ Basic ISAs of LoongArch: EnumValue Enum(isa_base) String(la64) Value(ISA_BASE_LA64V100) +EnumValue +Enum(isa_base) String(la64v1.1) Value(ISA_BASE_LA64V110) + ;; ISA extensions / adjustments Enum Name(isa_ext_fpu) Type(int) |