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| author | Wilco Dijkstra <wdijkstr@arm.com> | 2016-11-02 14:00:22 +0000 |
|---|---|---|
| committer | Wilco Dijkstra <wilco@gcc.gnu.org> | 2016-11-02 14:00:22 +0000 |
| commit | 5304d04437ac683b9a4c8207728db70774560222 (patch) | |
| tree | f7fccef0db51be2083c609129b09fee2d30222f1 /gcc | |
| parent | 45a6c1e36347998df5e779866f26d15dc9d01fbd (diff) | |
| download | gcc-5304d04437ac683b9a4c8207728db70774560222.zip gcc-5304d04437ac683b9a4c8207728db70774560222.tar.gz gcc-5304d04437ac683b9a4c8207728db70774560222.tar.bz2 | |
Add LE/BE SHA1H patterns with a V2SI input.
Add LE/BE SHA1H patterns with a V2SI input. This avoids unnecessary
DUPs when using intrinsics like vsha1h_u32 (vgetq_lane_u32 (x, 0)).
gcc/
* config/aarch64/aarch64-simd.md (aarch64_crypto_sha1hv4si):
New pattern.
(aarch64_be_crypto_sha1hv4si): New pattern.
From-SVN: r241791
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 20 |
2 files changed, 26 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 62211502..76b90a8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2016-11-26 Wilco Dijkstra <wdijkstr@arm.com> + + * config/aarch64/aarch64-simd.md (aarch64_crypto_sha1hv4si): + New pattern. + (aarch64_be_crypto_sha1hv4si): New pattern. + 2016-11-02 Wilco Dijkstra <wdijkstr@arm.com> * config/aarch64/aarch64.md (add<mode>3): Remove diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 9ce7f00..89bdcb3 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -5705,6 +5705,26 @@ [(set_attr "type" "crypto_sha1_fast")] ) +(define_insn "aarch64_crypto_sha1hv4si" + [(set (match_operand:SI 0 "register_operand" "=w") + (unspec:SI [(vec_select:SI (match_operand:V4SI 1 "register_operand" "w") + (parallel [(const_int 0)]))] + UNSPEC_SHA1H))] + "TARGET_SIMD && TARGET_CRYPTO && !BYTES_BIG_ENDIAN" + "sha1h\\t%s0, %s1" + [(set_attr "type" "crypto_sha1_fast")] +) + +(define_insn "aarch64_be_crypto_sha1hv4si" + [(set (match_operand:SI 0 "register_operand" "=w") + (unspec:SI [(vec_select:SI (match_operand:V4SI 1 "register_operand" "w") + (parallel [(const_int 3)]))] + UNSPEC_SHA1H))] + "TARGET_SIMD && TARGET_CRYPTO && BYTES_BIG_ENDIAN" + "sha1h\\t%s0, %s1" + [(set_attr "type" "crypto_sha1_fast")] +) + (define_insn "aarch64_crypto_sha1su1v4si" [(set (match_operand:V4SI 0 "register_operand" "=w") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") |