diff options
| author | Richard Sandiford <rsandifo@redhat.com> | 2004-08-23 08:20:53 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2004-08-23 08:20:53 +0000 |
| commit | 4d06ed0a96ce09cef95f80a7b2693410fb4a5da3 (patch) | |
| tree | 040b9959f05d232ccc92412f7eac22a6fa04321f /gcc | |
| parent | a3631d9785de39ffcf1925e71dc2fe017d17c448 (diff) | |
| download | gcc-4d06ed0a96ce09cef95f80a7b2693410fb4a5da3.zip gcc-4d06ed0a96ce09cef95f80a7b2693410fb4a5da3.tar.gz gcc-4d06ed0a96ce09cef95f80a7b2693410fb4a5da3.tar.bz2 | |
mips.md (length): Don't use mips_fetch_insns for indexed loads and stores.
* config/mips/mips.md (length): Don't use mips_fetch_insns for indexed
loads and stores.
(*lwxc1_<mode>, *ldxc1_<mode>, *swxc1_<mode>, *sdxc1_<mode>): Name
formerly unnamed patterns. Redefine using :P for the address. Remove
explicit length attributes.
From-SVN: r86419
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 88 |
2 files changed, 30 insertions, 66 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c68a2ed..ee5dde5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2004-08-23 Richard Sandiford <rsandifo@redhat.com> + + * config/mips/mips.md (length): Don't use mips_fetch_insns for indexed + loads and stores. + (*lwxc1_<mode>, *ldxc1_<mode>, *swxc1_<mode>, *sdxc1_<mode>): Name + formerly unnamed patterns. Redefine using :P for the address. Remove + explicit length attributes. + 2004-08-23 Zdenek Dvorak <rakdver@atrey.karlin.mff.cuni.cz> * tree-ssa-loop-im.c (fem_single_reachable_address, for_each_memref): diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index fa7ee20..e42a607 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -181,9 +181,9 @@ (eq_attr "type" "const") (symbol_ref "mips_const_insns (operands[1]) * 4") - (eq_attr "type" "load,fpload,fpidxload") + (eq_attr "type" "load,fpload") (symbol_ref "mips_fetch_insns (operands[1]) * 4") - (eq_attr "type" "store,fpstore,fpidxstore") + (eq_attr "type" "store,fpstore") (symbol_ref "mips_fetch_insns (operands[0]) * 4") ;; In the worst case, a call macro will take 8 instructions: @@ -3717,85 +3717,41 @@ beq\t%2,%.,1b\;\ ;; these instructions can only be used to load and store floating ;; point registers, that would probably cause trouble in reload. -(define_insn "" +(define_insn "*lwxc1_<mode>" [(set (match_operand:SF 0 "register_operand" "=f") - (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d") - (match_operand:SI 2 "register_operand" "d"))))] + (mem:SF (plus:P (match_operand:P 1 "register_operand" "d") + (match_operand:P 2 "register_operand" "d"))))] "ISA_HAS_FP4 && TARGET_HARD_FLOAT" "lwxc1\t%0,%1(%2)" - [(set_attr "type" "fpidxload") - (set_attr "mode" "SF") - (set_attr "length" "4")]) - -(define_insn "" - [(set (match_operand:SF 0 "register_operand" "=f") - (mem:SF (plus:DI (match_operand:DI 1 "register_operand" "d") - (match_operand:DI 2 "register_operand" "d"))))] - "ISA_HAS_FP4 && TARGET_HARD_FLOAT" - "lwxc1\t%0,%1(%2)" - [(set_attr "type" "fpidxload") - (set_attr "mode" "SF") - (set_attr "length" "4")]) - -(define_insn "" - [(set (match_operand:DF 0 "register_operand" "=f") - (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d") - (match_operand:SI 2 "register_operand" "d"))))] - "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" - "ldxc1\t%0,%1(%2)" - [(set_attr "type" "fpidxload") - (set_attr "mode" "DF") - (set_attr "length" "4")]) + [(set_attr "type" "fpidxload") + (set_attr "mode" "SF")]) -(define_insn "" +(define_insn "*ldxc1_<mode>" [(set (match_operand:DF 0 "register_operand" "=f") - (mem:DF (plus:DI (match_operand:DI 1 "register_operand" "d") - (match_operand:DI 2 "register_operand" "d"))))] + (mem:DF (plus:P (match_operand:P 1 "register_operand" "d") + (match_operand:P 2 "register_operand" "d"))))] "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "ldxc1\t%0,%1(%2)" - [(set_attr "type" "fpidxload") - (set_attr "mode" "DF") - (set_attr "length" "4")]) - -(define_insn "" - [(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d") - (match_operand:SI 2 "register_operand" "d"))) - (match_operand:SF 0 "register_operand" "f"))] - "ISA_HAS_FP4 && TARGET_HARD_FLOAT" - "swxc1\t%0,%1(%2)" - [(set_attr "type" "fpidxstore") - (set_attr "mode" "SF") - (set_attr "length" "4")]) + [(set_attr "type" "fpidxload") + (set_attr "mode" "DF")]) -(define_insn "" - [(set (mem:SF (plus:DI (match_operand:DI 1 "register_operand" "d") - (match_operand:DI 2 "register_operand" "d"))) +(define_insn "*swxc1_<mode>" + [(set (mem:SF (plus:P (match_operand:P 1 "register_operand" "d") + (match_operand:P 2 "register_operand" "d"))) (match_operand:SF 0 "register_operand" "f"))] "ISA_HAS_FP4 && TARGET_HARD_FLOAT" "swxc1\t%0,%1(%2)" - [(set_attr "type" "fpidxstore") - (set_attr "mode" "SF") - (set_attr "length" "4")]) - -(define_insn "" - [(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d") - (match_operand:SI 2 "register_operand" "d"))) - (match_operand:DF 0 "register_operand" "f"))] - "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" - "sdxc1\t%0,%1(%2)" - [(set_attr "type" "fpidxstore") - (set_attr "mode" "DF") - (set_attr "length" "4")]) + [(set_attr "type" "fpidxstore") + (set_attr "mode" "SF")]) -(define_insn "" - [(set (mem:DF (plus:DI (match_operand:DI 1 "register_operand" "d") - (match_operand:DI 2 "register_operand" "d"))) +(define_insn "*sdxc1_<mode>" + [(set (mem:DF (plus:P (match_operand:P 1 "register_operand" "d") + (match_operand:P 2 "register_operand" "d"))) (match_operand:DF 0 "register_operand" "f"))] "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "sdxc1\t%0,%1(%2)" - [(set_attr "type" "fpidxstore") - (set_attr "mode" "DF") - (set_attr "length" "4")]) + [(set_attr "type" "fpidxstore") + (set_attr "mode" "DF")]) ;; 16-bit Integer moves |