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| author | Mihailo Stojanovic <mistojanovic@wavecomp.com> | 2019-10-28 19:17:58 +0000 |
|---|---|---|
| committer | Jeff Law <law@gcc.gnu.org> | 2019-10-28 13:17:58 -0600 |
| commit | 48b2123f6336ba6c06846d7c8b60bd14eaeae7ec (patch) | |
| tree | c475946b9e5d38bc3cbd04ce95de88adae96ac1b /gcc | |
| parent | 420fb10c0974fcfa77d8a5146cc7d486ab423c1b (diff) | |
| download | gcc-48b2123f6336ba6c06846d7c8b60bd14eaeae7ec.zip gcc-48b2123f6336ba6c06846d7c8b60bd14eaeae7ec.tar.gz gcc-48b2123f6336ba6c06846d7c8b60bd14eaeae7ec.tar.bz2 | |
re PR target/82981 (unnecessary __multi3 call for mips64r6 linux kernel)
PR target/82981
* config/mips/mips.md (<u>mulditi3): Generate patterns for high
doubleword and low doubleword result of multiplication on
MIPS64R6.
* gcc.target/mips/mips64r6-ti-mult.c: New test.
From-SVN: r277537
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 15 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 3 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/mips/mips64r6-ti-mult.c | 16 |
4 files changed, 36 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0dfda99..691128e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2019-10-28 Mihailo Stojanovic <mistojanovic@wavecomp.com> + PR target/82981 + * config/mips/mips.md (<u>mulditi3): Generate patterns for high + doubleword and low doubleword result of multiplication on + MIPS64R6. + * config/mips/mips.c (DIRECT_BUILTIN_PURE): New macro. Add a pure qualifier to the built-in. (MSA_BUILTIN_PURE): New macro. Add a pure qualifier to the MSA diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 4ad5c62..658f5e6 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -2464,9 +2464,11 @@ [(set (match_operand:TI 0 "register_operand") (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand")) (any_extend:TI (match_operand:DI 2 "register_operand"))))] - "ISA_HAS_DMULT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)" + "ISA_HAS_R6DMUL + || (ISA_HAS_DMULT + && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120))" { - rtx hilo; + rtx hilo, hi, lo; if (TARGET_MIPS16) { @@ -2476,9 +2478,16 @@ } else if (TARGET_FIX_R4000) emit_insn (gen_<u>mulditi3_r4000 (operands[0], operands[1], operands[2])); - else + else if (ISA_HAS_DMULT) emit_insn (gen_<u>mulditi3_internal (operands[0], operands[1], operands[2])); + else + { + hi = mips_subword (operands[0], 1); + lo = mips_subword (operands[0], 0); + emit_insn (gen_muldi3_mul3_nohilo (lo, operands[1], operands[2])); + emit_insn (gen_<su>muldi3_highpart_r6 (hi, operands[1], operands[2])); + } DONE; }) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 06ca68a..76f1471 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,8 @@ 2019-10-28 Mihailo Stojanovic <mistojanovic@wavecomp.com> + PR target/82981 + * gcc.target/mips/mips64r6-ti-mult.c: New test. + * gcc.target/mips/mips-builtins-pure.c: New test. * gcc.target/mips/msa-insert-split.c: New test. diff --git a/gcc/testsuite/gcc.target/mips/mips64r6-ti-mult.c b/gcc/testsuite/gcc.target/mips/mips64r6-ti-mult.c new file mode 100644 index 0000000..f969e76 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mips64r6-ti-mult.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mabi=64 -march=mips64r6" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } } */ + +typedef unsigned __int128 u128; +typedef unsigned long long u64; + +u128 +test (u64 a, u64 b) +{ + return (u128)a * (u128)b; +} + +/* { dg-final { scan-assembler-not "__multi3" } } */ +/* { dg-final { scan-assembler "dmul" } } */ +/* { dg-final { scan-assembler "dmuhu" } } */ |