Daily bump.

7 files changed, 706 insertions, 1 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 380c7d9..dd5f765 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,409 @@
+2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
+
+	* doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
+	Add web-link to the avr-gcc wiki.
+
+2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
+
+	* doc/extend.texi (AVR Variable Attributes) [address]: Remove
+	documentation for a version without argument, which is not supported.
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* config/arm/arm_neon.h
+	(vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
+	(vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
+	(vld1_f16_x4, vld1_f32_x4): New.
+	(vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
+	(vld1_bf16_x4): New.
+	(vld1q_types_x4): Updated to use vld1q_x4
+	from arm_neon_builtins.def
+	* config/arm/arm_neon_builtins.def
+	(vld1_x4): Updated entries.
+	(vld1q_x4): New entries, but comes from the old vld1_x4
+	* config/arm/neon.md
+	(neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* config/arm/arm_neon.h
+	(vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
+	(vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
+	(vld1_f16_x3, vld1_f32_x3): New.
+	(vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
+	(vld1_bf16_x3): New.
+	(vld1q_types_x3): Updated to use vld1q_x3 from
+	arm_neon_builtins.def
+	* config/arm/arm_neon_builtins.def
+	(vld1_x3): Updated entries.
+	(vld1q_x3): New entries, but comes from the old vld1_x2
+	* config/arm/neon.md
+	(neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* config/arm/arm_neon.h
+	(vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
+	(vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
+	(vld1_f16_x2, vld1_f32_x2): New.
+	(vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
+	(vld1_bf16_x2): New.
+	(vld1q_types_x2): Updated to use vld1q_x2 from
+	arm_neon_builtins.def
+	* config/arm/arm_neon_builtins.def
+	(vld1_x2): Updated entries.
+	(vld1q_x2): New entries, but comes from the old vld1_x2
+	* config/arm/neon.md
+	(neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
+	neon_vld1_x2<mode>.
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* config/arm/arm_neon.h
+	(vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
+	(vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
+	(vst1q_f16_x4, vst1q_f32_x4): New.
+	(vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
+	(vst1q_bf16_x4): New.
+	* config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
+	* config/arm/neon.md
+	(neon_vst1q_x4<mode>): New.
+	(neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
+	* config/arm/unspecs.md
+	(UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* config/arm/arm_neon.h
+	(vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
+	(vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
+	(vst1q_f16_x3, vst1q_f32_x3): New.
+	(vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
+	(vst1q_bf16_x3): New.
+	* config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
+	* config/arm/neon.md
+	(neon_vst1q_x3<mode>): New.
+	(neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
+	* config/arm/unspecs.md
+	(UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* config/arm/arm_neon.h
+	(vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
+	(vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
+	(vst1q_f16_x2, vst1q_f32_x2): New.
+	(vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
+	(vst1q_bf16_x2): New.
+	* config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
+	* config/arm/neon.md
+	(neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
+	neon_vst1_x2<mode>.
+	* config/arm/iterators.md
+	(VMEMX2): New mode iterator.
+	(VMEMX2_q): New mode attribute.
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* config/arm/arm_neon.h
+	(vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
+	(vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
+	(vst1_f16_x4, vst1_f32_x4): New.
+	(vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
+	(vst1_bf16_x4): New.
+	* config/arm/arm_neon_builtins.def (vst1_x4): New entries.
+	* config/arm/neon.md (vst1_x4<mode>): New.
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* config/arm/arm_neon.h
+	(vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
+	(vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
+	(vst1_f16_x3, vst1_f32_x3): New.
+	(vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
+	(vst1_bf16_x3): New.
+	* config/arm/arm_neon_builtins.def (vst1_x3): New entries.
+	* config/arm/neon.md (vst1_x3<mode>): New.
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* config/arm/arm_neon.h
+	(vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
+	(vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
+	(vst1_f16_x2, vst1_f32_x2): New.
+	(vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
+	(vst1_bf16_x2): New.
+	* config/arm/arm_neon_builtins.def (vst1_x2): New entries.
+	* config/arm/neon.md (vst1_x2<mode>): New.
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* config/arm/arm_neon.h
+	(vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
+	(vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
+	(vld1q_f16_x4, vld1q_f32_x4): New.
+	(vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
+	(vld1q_bf16_x4): New.
+	* config/arm/arm_neon_builtins.def (vld1_x4): New entries.
+	* config/arm/neon.md
+	(neon_vld1_x4<mode>): New.
+	(neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
+	* config/arm/unspecs.md
+	(UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* config/arm/arm_neon.h
+	(vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
+	(vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
+	(vld1q_f16_x3, vld1q_f32_x3): New.
+	(vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
+	(vld1q_bf16_x3): New.
+	* config/arm/arm_neon_builtins.def (vld1_x3): New entries.
+	* config/arm/neon.md
+	(neon_vld1_x3<mode>): New.
+	(neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
+	* config/arm/unspecs.md
+	(UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* config/arm/arm_neon.h
+	(vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
+	(vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
+	(vld1q_f16_x2, vld1q_f32_x2): New.
+	(vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
+	(vld1q_bf16_x2): New.
+	* config/arm/arm_neon_builtins.def (vld1_x2): New entries.
+	* config/arm/neon.md (vld1_x2<mode>): New.
+
+2024-01-12  Tamar Christina  <tamar.christina@arm.com>
+
+	PR tree-optimization/113287
+	* doc/sourcebuild.texi (check_effective_target_bitint65535): New.
+
+2024-01-12  Tamar Christina  <tamar.christina@arm.com>
+
+	* tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
+	* tree-vect-loop.cc (vect_transform_loop): Likewise.
+
+2024-01-12  Tamar Christina  <tamar.christina@arm.com>
+
+	PR tree-optimization/113178
+	* tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
+	alternate exits.
+
+2024-01-12  Tamar Christina  <tamar.christina@arm.com>
+
+	PR tree-optimization/113237
+	* tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
+	existing LCSSA variable for exit when all exits are early break.
+
+2024-01-12  Tamar Christina  <tamar.christina@arm.com>
+
+	PR tree-optimization/113137
+	PR tree-optimization/113136
+	PR tree-optimization/113172
+	PR tree-optimization/113178
+	* tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
+	Maintain PHIs on inverted loops.
+	(vect_do_peeling): Maintain virtual PHIs on inverted loops.
+	* tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
+	latch.
+	(vect_create_loop_vinfo): Record all conds instead of only alt ones.
+
+2024-01-12  Tamar Christina  <tamar.christina@arm.com>
+
+	PR tree-optimization/113135
+	* tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
+	dependency analysis.
+
+2024-01-12  Iain Sandoe  <iain@sandoe.co.uk>
+
+	* config/rs6000/host-darwin.cc (segv_handler): Use the revised
+	diagnostics class member name for abort of error.
+
+2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
+
+	* config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
+	format string to %s argument.
+
+2024-01-12  John David Anglin  <danglin@gcc.gnu.org>
+	    Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/113182
+	* varasm.cc (process_pending_assemble_externals,
+	assemble_external_libcall): Use targetm.strip_name_encoding
+	before calling get_identifier.
+
+2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
+
+	PR target/113196
+	* config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
+	New member variable.
+	* config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
+	Declare.
+	* config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
+	* config/aarch64/aarch64-simd.md
+	(vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
+	(vec_unpack<su>_hi_<mode>): ...this.  Move the generation of
+	zip2 for zero-extends to...
+	(aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
+	instruction.  Fix big-endian handling.
+	(vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
+	(vec_unpack<su>_lo_<mode>): ...this.  Move the generation of
+	zip1 for zero-extends to...
+	(<optab><Vnarrowq><mode>2): ...a split of this instruction.
+	Fix big-endian handling.
+	(*aarch64_zip1_uxtl): New pattern.
+	(aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
+	(aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
+	* config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
+	(aarch64_gen_shareable_zero): Use it.
+	(aarch64_split_simd_shift_p): New function.
+
+2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
+	(function_beg_insn): New macro.
+	* function.cc (expand_function_start): Initialize function_beg_insn.
+
+2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
+
+	PR target/112989
+	* config/aarch64/aarch64-sve-builtins.h
+	(function_builder::m_overload_names): Replace with...
+	* config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
+	new global.
+	(add_overloaded_function): Update accordingly, using get_identifier
+	to get a GGC-friendly record of the name.
+
+2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
+
+	PR target/112989
+	* config/aarch64/aarch64-sve-builtins.def: Don't include
+	aarch64-sve-builtins-sme.def.
+	(DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
+	* config/aarch64/aarch64-sve-builtins-sme.def: ...here.
+	(DEF_SME_FUNCTION): New macro.  Use it and DEF_SME_FUNCTION_GS
+	instead of DEF_SVE_*.  Add AARCH64_FL_SME to anything that
+	requires AARCH64_FL_SME2.
+	* config/aarch64/aarch64-sve-builtins-sve2.def: Make same
+	AARCH64_FL_SME adjustment here.
+	* config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
+	include SME intrinsics.
+	(sme_function_groups): New array.
+	(handle_arm_sve_h): Remove check for AARCH64_FL_SME.
+	(handle_arm_sme_h): Use sme_function_groups instead of function_groups.
+
+2024-01-12  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	PR target/113281
+	* config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
+	(struct cpu_vector_cost): Add regmove struct.
+	(get_vector_costs): Export as global.
+	* config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
+	(costs::add_stmt_cost): Ditto.
+	* config/riscv/riscv.cc (get_common_costs): Export global function.
+
+2024-01-12  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/113334
+	* gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
+	wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
+	to determine if number should be extended by all ones rather than zero
+	extended.
+
+2024-01-12  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/113330
+	* tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
+	too large size.
+
+2024-01-12  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/113323
+	* gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
+	check for lhs being large/huge _BitInt not in m_names.
+
+2024-01-12  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/113316
+	* gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
+	uninitialized large/huge _BitInt arguments to calls.
+
+2024-01-12  Jakub Jelinek  <jakub@redhat.com>
+
+	* gimple-lower-bitint.cc (mergeable_op): Instead of comparing
+	TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
+	CEIL (TYPE_PRECISION (t), limb_prec).
+	(bitint_large_huge::handle_cast): Likewise.
+
+2024-01-12  Ilya Leoshkevich  <iii@linux.ibm.com>
+
+	PR sanitizer/113284
+	* config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
+	Use assemble_function_label_final () for Power ELF V1 ABI.
+	* output.h (assemble_function_label_final): New function.
+	* varasm.cc (assemble_function_label_raw): Use
+	assemble_function_label_final ().
+	(assemble_function_label_final): New function.
+
+2024-01-12  Richard Biener  <rguenther@suse.de>
+
+	PR middle-end/113344
+	* match.pd ((double)float CMP (double)float -> float CMP float):
+	Perform result type check only for vectors.
+	* fold-const.cc (fold_binary_loc): Likewise.
+
+2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>
+
+	* config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
+	(usdot_prod<mode>): Ditto.
+	(sdot_prod<mode>): Ditto.
+	(udot_prod<mode>): Ditto.
+
+2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>
+
+	PR target/113288
+	* config/i386/i386-c.cc (ix86_target_macros_internal):
+	Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
+
+2024-01-12  Richard Biener  <rguenther@suse.de>
+
+	PR target/112280
+	* config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
+	Do not generate code when d.testing_p.
+
+2024-01-12  liuhongt  <hongtao.liu@intel.com>
+
+	PR target/113039
+	* doc/invoke.texi (fcf-protection=): Update documents.
+
+2024-01-12  Pan Li  <pan2.li@intel.com>
+
+	* config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
+	comments of predicate func riscv_v_ext_mode_p.
+
+2024-01-12  Feng Wang  <wangfeng@eswincomputing.com>
+
+	* config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
+			Modify ABI-name length of vfloat16m8_t
+
+2024-01-12  Li Wei  <liwei@loongson.cn>
+
+	* config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
+	Adjust.
+
+2024-01-12  Li Wei  <liwei@loongson.cn>
+
+	* config/loongarch/loongarch.md (add<mode>3): Removed.
+	(*addsi3): New.
+	(addsi3): Ditto.
+	(adddi3): Ditto.
+	(*addsi3_extended): Removed.
+	(addsi3_extended): New.
+
 2024-01-11  Jin Ma  <jinma@linux.alibaba.com>
 
 	* config/riscv/thead.md: Add limits for splits.
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 8f71cba..f550188 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20240112
+20240113
diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog
index e312398..e7bcd95 100644
--- a/gcc/c/ChangeLog
+++ b/gcc/c/ChangeLog
@@ -1,3 +1,9 @@
+2024-01-12  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/113315
+	* c-typeck.cc (build_array_ref): If index has BITINT_TYPE type with
+	precision larger than sizetype precision, convert it to sizetype.
+
 2024-01-11  Julian Brown  <julian@codesourcery.com>
 
 	* c-parser.cc (c_parser_braced_init, c_parser_conditional_expression):
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 6fc59fc..69883bf 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,22 @@
+2024-01-12  Jason Merrill  <jason@redhat.com>
+
+	PR c++/113038
+	* name-lookup.cc (lookup_elaborated_type): Look for bindings
+	in the global namespace in the ABI namespace.
+
+2024-01-12  Jason Merrill  <jason@redhat.com>
+
+	* call.cc (reversed_match): New.
+	(enum class pmatch): New enum.
+	(cand_parms_match): Add match_kind parm.
+	(object_parms_correspond): Add fn parms.
+	(joust): Adjust.
+	* class.cc (xobj_iobj_parameters_correspond): Rename to...
+	(iobj_parm_corresponds_to): ...this.  Take the other
+	type instead of a second function.
+	(object_parms_correspond): Adjust.
+	* cp-tree.h (iobj_parm_corresponds_to): Declare.
+
 2024-01-11  Jason Merrill  <jason@redhat.com>
 
 	PR c++/113191
diff --git a/gcc/jit/ChangeLog b/gcc/jit/ChangeLog
index b53c7e1..d233b7d 100644
--- a/gcc/jit/ChangeLog
+++ b/gcc/jit/ChangeLog
@@ -1,3 +1,55 @@
+2024-01-12  Guillaume Gomez  <guillaume1.gomez@gmail.com>
+	    Antoni Boucher  <bouanto@zoho.com>
+
+	* docs/topics/compatibility.rst: Add documentation for LIBGCCJIT_ABI_26.
+	* docs/topics/functions.rst: Add documentation for new functions.
+	* docs/topics/expressions.rst: Add documentation for new functions.
+
+2024-01-12  Guillaume Gomez  <guillaume1.gomez@gmail.com>
+	    Antoni Boucher  <bouanto@zoho.com>
+
+	* dummy-frontend.cc (handle_alias_attribute): New function.
+	(handle_always_inline_attribute): New function.
+	(handle_cold_attribute): New function.
+	(handle_fnspec_attribute): New function.
+	(handle_format_arg_attribute): New function.
+	(handle_format_attribute): New function.
+	(handle_noinline_attribute): New function.
+	(handle_target_attribute): New function.
+	(handle_used_attribute): New function.
+	(handle_visibility_attribute): New function.
+	(handle_weak_attribute): New function.
+	(handle_alias_ifunc_attribute): New function.
+	* jit-playback.cc (fn_attribute_to_string): New function.
+	(variable_attribute_to_string): New function.
+	(global_new_decl): Add attributes support.
+	(set_variable_attribute): New function.
+	(new_global): Add attributes support.
+	(new_global_initialized): Add attributes support.
+	(new_local): Add attributes support.
+	* jit-playback.h (fn_attribute_to_string): New function.
+	(set_variable_attribute): New function.
+	* jit-recording.cc (recording::lvalue::add_attribute): New function.
+	(recording::function::function): New function.
+	(recording::function::write_to_dump): Add attributes support.
+	(recording::function::add_attribute): New function.
+	(recording::function::add_string_attribute): New function.
+	(recording::function::add_integer_array_attribute): New function.
+	(recording::global::replay_into): Add attributes support.
+	(recording::local::replay_into): Add attributes support.
+	* jit-recording.h: Add attributes support.
+	* libgccjit.cc (gcc_jit_function_add_attribute): New function.
+	(gcc_jit_function_add_string_attribute): New function.
+	(gcc_jit_function_add_integer_array_attribute): New function.
+	(gcc_jit_lvalue_add_attribute): New function.
+	* libgccjit.h (enum gcc_jit_fn_attribute): New enum.
+	(gcc_jit_function_add_attribute): New function.
+	(gcc_jit_function_add_string_attribute): New function.
+	(gcc_jit_function_add_integer_array_attribute): New function.
+	(enum gcc_jit_variable_attribute): New function.
+	(gcc_jit_lvalue_add_string_attribute): New function.
+	* libgccjit.map: Declare new functions.
+
 2023-12-06  David Malcolm  <dmalcolm@redhat.com>
 
 	* dummy-frontend.cc (jit_begin_diagnostic): Make diagnostic_info
diff --git a/gcc/objc/ChangeLog b/gcc/objc/ChangeLog
index 2a50fa0..7e61c71 100644
--- a/gcc/objc/ChangeLog
+++ b/gcc/objc/ChangeLog
@@ -1,3 +1,9 @@
+2024-01-12  Iain Sandoe  <iain@sandoe.co.uk>
+
+	* objc-next-runtime-abi-02.cc
+	(build_v2_objc_method_fixup_call): Early exit for cases
+	where the sender or receiver are known to be in error.
+
 2023-11-27  Alex Coplan  <alex.coplan@arm.com>
 	    Iain Sandoe  <iain@sandoe.co.uk>
 
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 5c68073..5fc14bf 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,219 @@
+2024-01-12  Jason Merrill  <jason@redhat.com>
+
+	PR c++/113038
+	* g++.dg/modules/pr106304_b.C: Add dynamic_cast.
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* gcc.target/arm/simd/vld1_base_xN_1.c: Updated.
+	* gcc.target/arm/simd/vld1_bf16_xN_1.c: Updated.
+	* gcc.target/arm/simd/vld1_fp16_xN_1.c: Updated.
+	* gcc.target/arm/simd/vld1_p64_xN_1.c: Updated.
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* gcc.target/arm/simd/vld1_base_xN_1.c: Updated.
+	* gcc.target/arm/simd/vld1_bf16_xN_1.c: Updated.
+	* gcc.target/arm/simd/vld1_fp16_xN_1.c: Updated.
+	* gcc.target/arm/simd/vld1_p64_xN_1.c: Updated.
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* gcc.target/arm/simd/vld1_base_xN_1.c: Add new tests.
+	* gcc.target/arm/simd/vld1_bf16_xN_1.c: Add new tests.
+	* gcc.target/arm/simd/vld1_fp16_xN_1.c: Add new tests.
+	* gcc.target/arm/simd/vld1_p64_xN_1.c: Add new tests.
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* gcc.target/arm/simd/vst1q_base_xN_1.c: Updated
+	* gcc.target/arm/simd/vst1q_bf16_xN_1.c: Updated
+	* gcc.target/arm/simd/vst1q_fp16_xN_1.c: Updated
+	* gcc.target/arm/simd/vst1q_p64_xN_1.c: Updated
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* gcc.target/arm/simd/vst1q_base_xN_1.c: Add new tests.
+	* gcc.target/arm/simd/vst1q_bf16_xN_1.c: Add new tests.
+	* gcc.target/arm/simd/vst1q_fp16_xN_1.c: Add new tests.
+	* gcc.target/arm/simd/vst1q_p64_xN_1.c: Add new tests.
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* gcc.target/arm/simd/vst1q_base_xN_1.c: Add new tests.
+	* gcc.target/arm/simd/vst1q_bf16_xN_1.c: Add new tests.
+	* gcc.target/arm/simd/vst1q_fp16_xN_1.c: Add new tests.
+	* gcc.target/arm/simd/vst1q_p64_xN_1.c: Add new tests.
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* gcc.target/arm/simd/vst1_base_xN_1.c: Updated.
+	* gcc.target/arm/simd/vst1_bf16_xN_1.c: Updated.
+	* gcc.target/arm/simd/vst1_fp16_xN_1.c: Updated.
+	* gcc.target/arm/simd/vst1_p64_xN_1.c: Updated.
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* gcc.target/arm/simd/vst1_base_xN_1.c: Updated.
+	* gcc.target/arm/simd/vst1_bf16_xN_1.c: Updated.
+	* gcc.target/arm/simd/vst1_fp16_xN_1.c: Updated.
+	* gcc.target/arm/simd/vst1_p64_xN_1.c: Updated.
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* gcc.target/arm/simd/vst1_base_xN_1.c: Add new tests.
+	* gcc.target/arm/simd/vst1_bf16_xN_1.c: Add new tests.
+	* gcc.target/arm/simd/vst1_fp16_xN_1.c: Add new tests.
+	* gcc.target/arm/simd/vst1_p64_xN_1.c: Add new tests.
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* gcc.target/arm/simd/vld1q_base_xN_1.c: Updated.
+	* gcc.target/arm/simd/vld1q_bf16_xN_1.c: Updated.
+	* gcc.target/arm/simd/vld1q_fp16_xN_1.c: Updated.
+	* gcc.target/arm/simd/vld1q_p64_xN_1.c: Updated.
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* gcc.target/arm/simd/vld1q_base_xN_1.c: Add new tests.
+	* gcc.target/arm/simd/vld1q_bf16_xN_1.c: Add new tests.
+	* gcc.target/arm/simd/vld1q_fp16_xN_1.c: Add new tests.
+	* gcc.target/arm/simd/vld1q_p64_xN_1.c: Add new tests.
+
+2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
+
+	* gcc.target/arm/simd/vld1q_base_xN_1.c: Add new test.
+	* gcc.target/arm/simd/vld1q_bf16_xN_1.c: Add new test.
+	* gcc.target/arm/simd/vld1q_fp16_xN_1.c: Add new test.
+	* gcc.target/arm/simd/vld1q_p64_xN_1.c: Add new test.
+
+2024-01-12  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/113315
+	* gcc.dg/bitint-65.c: New test.
+	* gcc.dg/bitint-66.c: New test.
+
+2024-01-12  Tamar Christina  <tamar.christina@arm.com>
+
+	PR tree-optimization/113287
+	* gcc.dg/vect/vect-early-break_100-pr113287.c: Support non-bitint.
+	* gcc.dg/vect/vect-early-break_99-pr113287.c: Likewise.
+	* lib/target-supports.exp (bitint, bitint128, bitint575, bitint65535):
+	Document them.
+
+2024-01-12  Tamar Christina  <tamar.christina@arm.com>
+
+	PR tree-optimization/113178
+	* gcc.dg/vect/vect-early-break_101-pr113178.c: New test.
+	* gcc.dg/vect/vect-early-break_102-pr113178.c: New test.
+
+2024-01-12  Tamar Christina  <tamar.christina@arm.com>
+
+	PR tree-optimization/113237
+	* gcc.dg/vect/vect-early-break_98-pr113237.c: New test.
+
+2024-01-12  Tamar Christina  <tamar.christina@arm.com>
+
+	PR tree-optimization/113137
+	PR tree-optimization/113136
+	PR tree-optimization/113172
+	PR tree-optimization/113178
+	* g++.dg/vect/vect-early-break_4-pr113137.cc: New test.
+	* g++.dg/vect/vect-early-break_5-pr113137.cc: New test.
+	* gcc.dg/vect/vect-early-break_95-pr113137.c: New test.
+	* gcc.dg/vect/vect-early-break_96-pr113136.c: New test.
+	* gcc.dg/vect/vect-early-break_97-pr113172.c: New test.
+
+2024-01-12  Tamar Christina  <tamar.christina@arm.com>
+
+	PR tree-optimization/113135
+	* gcc.dg/vect/vect-early-break_103-pr113135.c: New test.
+
+2024-01-12  Jason Merrill  <jason@redhat.com>
+
+	* g++.dg/cpp2a/concepts-memfun4.C: Change expected
+	reversed handling.
+
+2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
+
+	PR target/113196
+	* gcc.target/aarch64/pr113196.c: New test.
+	* gcc.target/aarch64/simd/vmovl_high_1.c: Remove double include.
+	Expect uxtl2 rather than zip2.
+	* gcc.target/aarch64/vect_mixed_sizes_8.c: Expect zip1 rather
+	than uxtl.
+	* gcc.target/aarch64/vect_mixed_sizes_9.c: Likewise.
+	* gcc.target/aarch64/vect_mixed_sizes_10.c: Likewise.
+
+2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
+
+	PR target/112989
+	* gcc.target/aarch64/sve/acle/general-c/clamp_1.c: Remove bogus
+	error test.
+
+2024-01-12  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	PR target/113281
+	* gcc.target/riscv/rvv/autovec/pr113209.c: Adapt test.
+	* gcc.dg/vect/costmodel/riscv/rvv/pr113281-1.c: New test.
+	* gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c: New test.
+
+2024-01-12  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/113334
+	* gcc.dg/torture/bitint-46.c: New test.
+
+2024-01-12  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/113330
+	* gcc.dg/bitint-69.c: New test.
+
+2024-01-12  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/113323
+	* gcc.dg/bitint-68.c: New test.
+
+2024-01-12  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/113316
+	* gcc.dg/bitint-67.c: New test.
+
+2024-01-12  Guillaume Gomez  <guillaume1.gomez@gmail.com>
+	    Antoni Boucher  <bouanto@zoho.com>
+
+	* jit.dg/all-non-failing-tests.h: Add new attributes tests.
+	* jit.dg/jit.exp: Add `jit-verify-assembler-output-not` test command.
+	* jit.dg/test-restrict-attribute.c: New test.
+	* jit.dg/test-alias-attribute.c: New test.
+	* jit.dg/test-always_inline-attribute.c: New test.
+	* jit.dg/test-cold-attribute.c: New test.
+	* jit.dg/test-const-attribute.c: New test.
+	* jit.dg/test-noinline-attribute.c: New test.
+	* jit.dg/test-nonnull-attribute.c: New test.
+	* jit.dg/test-pure-attribute.c: New test.
+	* jit.dg/test-used-attribute.c: New test.
+	* jit.dg/test-variable-attribute.c: New test.
+	* jit.dg/test-weak-attribute.c: New test.
+
+2024-01-12  Jakub Jelinek  <jakub@redhat.com>
+
+	* gcc.dg/bitint-31.c: Fix up #if conditions checking whether
+	__*_MANT_DIG__ is equal to a particular precision.
+
+2024-01-12  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	* gcc.target/riscv/rvv/autovec/fold-min-poly.c: Remove -fno-vect-cost-model
+
+2024-01-12  Li Wei  <liwei@loongson.cn>
+
+	* gcc.target/loongarch/sign-extend-2.c: Adjust.
+
+2024-01-12  Li Wei  <liwei@loongson.cn>
+
+	* gcc.target/loongarch/sign-extend.c: Moved to...
+	* gcc.target/loongarch/sign-extend-1.c: ...here.
+	* gcc.target/loongarch/sign-extend-2.c: New test.
+
 2024-01-11  Julian Brown  <julian@codesourcery.com>
 
 	* gcc.dg/gomp/bad-array-section-c-1.c: New test.