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author | Pan Li <pan2.li@intel.com> | 2023-06-14 10:10:44 +0800 |
---|---|---|
committer | Pan Li <pan2.li@intel.com> | 2023-06-15 09:06:29 +0800 |
commit | 41738a1b3f333d0283fe911f715194f602d318f6 (patch) | |
tree | b1144e42ad87697b53d1b5b137f85c72ed7ae54d /gcc | |
parent | 8a3a4fb273f9c69b8f9f6c303508610d34b3ebf1 (diff) | |
download | gcc-41738a1b3f333d0283fe911f715194f602d318f6.zip gcc-41738a1b3f333d0283fe911f715194f602d318f6.tar.gz gcc-41738a1b3f333d0283fe911f715194f602d318f6.tar.bz2 |
RISC-V: Align the predictor style for define_insn_and_split
This patch is considered as the follow up of the below PATCH.
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621347.html
We aligned the predictor style for the define_insn_and_split suggested
by Kito. To avoid potential issues before we hit.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/autovec-opt.md: Align the predictor sytle.
* config/riscv/autovec.md: Ditto.
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/config/riscv/autovec-opt.md | 20 | ||||
-rw-r--r-- | gcc/config/riscv/autovec.md | 24 |
2 files changed, 22 insertions, 22 deletions
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index aef28e4..fb1b072 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -37,9 +37,9 @@ (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")) (match_operand:VWEXTI 3 "register_operand" " vr, vr")) (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred_vf2 (<CODE>, <MODE>mode); @@ -132,9 +132,9 @@ (bitmanip_bitwise:VB (not:VB (match_operand:VB 2 "register_operand" " vr")) (match_operand:VB 1 "register_operand" " vr")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred_not (<CODE>, <MODE>mode); @@ -159,9 +159,9 @@ (any_bitwise:VB (match_operand:VB 1 "register_operand" " vr") (match_operand:VB 2 "register_operand" " vr"))))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred_n (<CODE>, <MODE>mode); @@ -346,9 +346,9 @@ (match_operand:VWEXTI 1 "register_operand" " vr,vr") (any_extend:VWEXTI (match_operand:<V_DOUBLE_TRUNC> 2 "vector_shift_operand" " vr,vk")))))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred_narrow (<any_shiftrt:CODE>, <MODE>mode); @@ -364,9 +364,9 @@ (any_shiftrt:VWEXTI (match_operand:VWEXTI 1 "register_operand" " vr") (match_operand:<VEL> 2 "csr_operand" " rK"))))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { operands[2] = gen_lowpart (Pmode, operands[2]); diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index eadc2c5..c23a625 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -155,9 +155,9 @@ (any_shift:VI (match_operand:VI 1 "register_operand" " vr") (match_operand:<VEL> 2 "csr_operand" " rK")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { operands[2] = gen_lowpart (Pmode, operands[2]); @@ -180,9 +180,9 @@ (any_shift:VI (match_operand:VI 1 "register_operand" " vr,vr") (match_operand:VI 2 "vector_shift_operand" " vr,vk")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode), @@ -205,9 +205,9 @@ [(set (match_operand:VB 0 "register_operand" "=vr") (any_bitwise:VB (match_operand:VB 1 "register_operand" " vr") (match_operand:VB 2 "register_operand" " vr")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred (<CODE>, <MODE>mode); @@ -227,9 +227,9 @@ (define_insn_and_split "one_cmpl<mode>2" [(set (match_operand:VB 0 "register_operand" "=vr") (not:VB (match_operand:VB 1 "register_operand" " vr")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred_not (<MODE>mode); @@ -366,9 +366,9 @@ [(set (match_operand:VWEXTI 0 "register_operand" "=&vr") (any_extend:VWEXTI (match_operand:<V_DOUBLE_TRUNC> 1 "register_operand" "vr")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred_vf2 (<CODE>, <MODE>mode); @@ -409,9 +409,9 @@ [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vr") (truncate:<V_DOUBLE_TRUNC> (match_operand:VWEXTI 1 "register_operand" " vr")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred_trunc (<MODE>mode); |