Fix PR 47408 and 47385

From-SVN: r169167

17 files changed, 41 insertions, 16 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7f3148a..d13b627 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2011-01-24  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	PR target/47385
+	* config/rs6000/altivec.md (vector constant splitters): Add
+	support for creating vector single precision constants if -mvsx is
+	used and we would create the constant using Altivec primitives.
+
 2011-01-23  Bernd Schmidt  <bernds@codesourcery.com>
 	    Richard Sandiford  <rdsandiford@googlemail.com>
 
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index b7819f5..d21d576 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -224,7 +224,7 @@
 (define_split
   [(set (match_operand:VM 0 "altivec_register_operand" "")
 	(match_operand:VM 1 "easy_vector_constant_msb" ""))]
-  "VECTOR_UNIT_ALTIVEC_P (<MODE>mode) && reload_completed"
+  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && reload_completed"
   [(const_int 0)]
 {
   rtx dest = operands[0];
@@ -251,7 +251,7 @@
 (define_split
   [(set (match_operand:VM 0 "altivec_register_operand" "")
 	(match_operand:VM 1 "easy_vector_constant_add_self" ""))]
-  "VECTOR_UNIT_ALTIVEC_P (<MODE>mode) && reload_completed"
+  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && reload_completed"
   [(set (match_dup 0) (match_dup 3))
    (set (match_dup 0) (match_dup 4))]
 {
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 33d1cda..d9b1f19 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,21 @@
+2011-01-24  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	PR target/47408
+	* gcc.target/powerpc/altivec-11.c: Add explicit -mno-vsx.
+	* gcc.target/powerpc/altivec-14.c: Ditto.
+	* gcc.target/powerpc/altivec-33.c: Ditto.
+	* gcc.target/powerpc/altivec-types-1.c: Ditto.
+	* gcc.target/powerpc/altivec-types-2.c: Ditto.
+	* gcc.target/powerpc/altivec-types-3.c: Ditto.
+	* gcc.target/powerpc/altivec-types-4.c: Ditto.
+	* gcc.target/powerpc/ppc-vector-memcpy.c: Ditto.
+	* gcc.target/powerpc/ppc-vector-memset.c: Ditto.
+	* g++.dg/ext/altivec-15.C: Ditto.
+	* g++.dg/ext/altivec-types-1.C: Ditto.
+	* g++.dg/ext/altivec-types-2.C: Ditto.
+	* g++.dg/ext/altivec-types-3.C: Ditto.
+	* g++.dg/ext/altivec-types-4.C: Ditto.
+
 2011-01-24  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
 
 	* lib/scanasm.exp (dg-function-on-line): Handle mips-sgi-irix*.
diff --git a/gcc/testsuite/g++.dg/ext/altivec-15.C b/gcc/testsuite/g++.dg/ext/altivec-15.C
index ed1c088..d8e982d 100644
--- a/gcc/testsuite/g++.dg/ext/altivec-15.C
+++ b/gcc/testsuite/g++.dg/ext/altivec-15.C
@@ -1,6 +1,6 @@
 /* { dg-do compile { target powerpc*-*-* } } */
 /* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec" } */
+/* { dg-options "-maltivec -mno-vsx" } */
 
 /* This test was added for an internal compiler error.  The number and
    content of error messages is irrelevant.  */
diff --git a/gcc/testsuite/g++.dg/ext/altivec-types-1.C b/gcc/testsuite/g++.dg/ext/altivec-types-1.C
index 710ce4b..f54aeec 100644
--- a/gcc/testsuite/g++.dg/ext/altivec-types-1.C
+++ b/gcc/testsuite/g++.dg/ext/altivec-types-1.C
@@ -1,6 +1,6 @@
 /* { dg-do compile { target powerpc*-*-linux* } } */
 /* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec -std=c++98" } */
+/* { dg-options "-maltivec -mno-vsx -std=c++98" } */
 
 /* Valid AltiVec vector types should be accepted with no warnings.  */
 
diff --git a/gcc/testsuite/g++.dg/ext/altivec-types-2.C b/gcc/testsuite/g++.dg/ext/altivec-types-2.C
index f64c0c5..cee6c8f 100644
--- a/gcc/testsuite/g++.dg/ext/altivec-types-2.C
+++ b/gcc/testsuite/g++.dg/ext/altivec-types-2.C
@@ -1,7 +1,7 @@
 /* { dg-do compile { target powerpc*-*-linux* } } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec" } */
+/* { dg-options "-maltivec -mno-vsx" } */
 
 /* These should get warnings for 32-bit code.  */
 
diff --git a/gcc/testsuite/g++.dg/ext/altivec-types-3.C b/gcc/testsuite/g++.dg/ext/altivec-types-3.C
index 2fe9659..6bea9a1 100644
--- a/gcc/testsuite/g++.dg/ext/altivec-types-3.C
+++ b/gcc/testsuite/g++.dg/ext/altivec-types-3.C
@@ -1,7 +1,7 @@
 /* { dg-do compile { target powerpc*-*-linux* } } */
 /* { dg-require-effective-target powerpc_altivec_ok } */
 /* { dg-require-effective-target lp64 } */
-/* { dg-options "-maltivec" } */
+/* { dg-options "-maltivec -mno-vsx" } */
 
 /* These should be rejected for 64-bit code.  */
 
diff --git a/gcc/testsuite/g++.dg/ext/altivec-types-4.C b/gcc/testsuite/g++.dg/ext/altivec-types-4.C
index 212f673..b937f3c 100644
--- a/gcc/testsuite/g++.dg/ext/altivec-types-4.C
+++ b/gcc/testsuite/g++.dg/ext/altivec-types-4.C
@@ -1,7 +1,7 @@
 /* { dg-do compile { target powerpc*-*-linux* } } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec -mno-warn-altivec-long" } */
+/* { dg-options "-maltivec -mno-vsx -mno-warn-altivec-long" } */
 
 /* These should not get warnings for 32-bit code when the warning is
    disabled.  */
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-11.c b/gcc/testsuite/gcc.target/powerpc/altivec-11.c
index 648993a..7e3510c 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-11.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-11.c
@@ -1,6 +1,6 @@
 /* { dg-do compile { target powerpc*-*-* } } */
 /* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-O2 -maltivec -mabi=altivec" } */
+/* { dg-options "-O2 -maltivec -mno-vsx -mabi=altivec" } */
 /* { dg-final { scan-assembler-not "lvx" } } */
 #include <altivec.h>
 
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-14.c b/gcc/testsuite/gcc.target/powerpc/altivec-14.c
index 4d3cf4f..55acb0b 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-14.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-14.c
@@ -1,6 +1,6 @@
 /* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */
 /* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec" } */
+/* { dg-options "-maltivec -mno-vsx" } */
 
 #include <altivec.h>
 
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-33.c b/gcc/testsuite/gcc.target/powerpc/altivec-33.c
index c1c935a..8e912679 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-33.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-33.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-O2 -maltivec" } */
+/* { dg-options "-O2 -maltivec -mno-vsx" } */
 
 /* We should only produce one vspltw as we already splatted the value.  */
 /* { dg-final { scan-assembler-times "vspltw" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-types-1.c b/gcc/testsuite/gcc.target/powerpc/altivec-types-1.c
index 41de952..9096892 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-types-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-types-1.c
@@ -1,6 +1,6 @@
 /* { dg-do compile { target powerpc*-*-linux* } } */
 /* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec" } */
+/* { dg-options "-maltivec -mno-vsx" } */
 
 /* Valid AltiVec vector types should be accepted with no warnings.  */
 
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-types-2.c b/gcc/testsuite/gcc.target/powerpc/altivec-types-2.c
index f64c0c5..cee6c8f 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-types-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-types-2.c
@@ -1,7 +1,7 @@
 /* { dg-do compile { target powerpc*-*-linux* } } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec" } */
+/* { dg-options "-maltivec -mno-vsx" } */
 
 /* These should get warnings for 32-bit code.  */
 
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-types-3.c b/gcc/testsuite/gcc.target/powerpc/altivec-types-3.c
index 38c4d6c..ea371ce 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-types-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-types-3.c
@@ -1,7 +1,7 @@
 /* { dg-do compile { target powerpc*-*-linux* } } */
 /* { dg-require-effective-target lp64 } */
 /* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec" } */
+/* { dg-options "-maltivec -mno-vsx" } */
 
 /* These should be rejected for 64-bit code.  */
 
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-types-4.c b/gcc/testsuite/gcc.target/powerpc/altivec-types-4.c
index 212f673..52fa914 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-types-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-types-4.c
@@ -1,7 +1,7 @@
 /* { dg-do compile { target powerpc*-*-linux* } } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec -mno-warn-altivec-long" } */
+/* { dg-options "-maltivec -mno-warn-altivec-long -mno-vsx" } */
 
 /* These should not get warnings for 32-bit code when the warning is
    disabled.  */
diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-vector-memcpy.c b/gcc/testsuite/gcc.target/powerpc/ppc-vector-memcpy.c
index a9a16ab..797c407 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc-vector-memcpy.c
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-vector-memcpy.c
@@ -1,6 +1,6 @@
 /* { dg-do compile { target powerpc*-*-* } } */
 /* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-O -maltivec" } */
+/* { dg-options "-O -maltivec -mno-vsx" } */
 /* { dg-final { scan-assembler "lvx" } } */
 
 void foo(void)
diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-vector-memset.c b/gcc/testsuite/gcc.target/powerpc/ppc-vector-memset.c
index 1a29071..ad7aade 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc-vector-memset.c
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-vector-memset.c
@@ -1,6 +1,6 @@
 /* { dg-do compile { target powerpc*-*-* } } */
 /* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-O -maltivec" } */
+/* { dg-options "-O -maltivec -mno-vsx" } */
 /* { dg-final { scan-assembler "stvx" } } */
 
 #include <string.h>