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| author | Claudiu Zissulescu <claziss@synopsys.com> | 2017-07-17 14:59:56 +0200 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@gcc.gnu.org> | 2017-07-17 14:59:56 +0200 |
| commit | 3f2fc95cd80c7d45074532bdb4120cb4276f6249 (patch) | |
| tree | c8d2ee2c9bf97f9fa6cda97eff76cf22910ee052 /gcc | |
| parent | ac66951af8de1aea9af3c10c4e5b08cce8bc209c (diff) | |
| download | gcc-3f2fc95cd80c7d45074532bdb4120cb4276f6249.zip gcc-3f2fc95cd80c7d45074532bdb4120cb4276f6249.tar.gz gcc-3f2fc95cd80c7d45074532bdb4120cb4276f6249.tar.bz2 | |
[ARC] Deprecate mexpand-adddi option.
Emitting subregs in the expand will result in broken code due to LRA handling of them. Issue observed while turning on mlra and mexpand-adddi options using dejagnu test suite. Deprecate this
option.
gcc/
2017-04-26 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.md (adddi3): Remove support for mexpand-adddi
option.
(subdi3): Likewise.
* config/arc/arc.opt (mexpand-adddi): Deprecate it.
* doc/invoke.texi (mexpand-adddi): Update text.
From-SVN: r250276
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/arc/arc.md | 39 | ||||
| -rw-r--r-- | gcc/config/arc/arc.opt | 2 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 2 |
4 files changed, 11 insertions, 40 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0bbebc8..5e28c1a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,13 @@ 2017-07-17 Claudiu Zissulescu <claziss@synopsys.com> + * config/arc/arc.md (adddi3): Remove support for mexpand-adddi + option. + (subdi3): Likewise. + * config/arc/arc.opt (mexpand-adddi): Deprecate it. + * doc/invoke.texi (mexpand-adddi): Update text. + +2017-07-17 Claudiu Zissulescu <claziss@synopsys.com> + * config/arc/arc.md (clzsi2): Expand to an arc_clzsi2 instruction that also clobbers the CC register. The old expand code is moved to ... diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 630c84a..6fb0f17 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -2649,30 +2649,7 @@ (match_operand:DI 2 "nonmemory_operand" ""))) (clobber (reg:CC CC_REG))])] "" -{ - if (TARGET_EXPAND_ADDDI) - { - rtx l0 = gen_lowpart (SImode, operands[0]); - rtx h0 = disi_highpart (operands[0]); - rtx l1 = gen_lowpart (SImode, operands[1]); - rtx h1 = disi_highpart (operands[1]); - rtx l2 = gen_lowpart (SImode, operands[2]); - rtx h2 = disi_highpart (operands[2]); - rtx cc_c = gen_rtx_REG (CC_Cmode, CC_REG); - - if (CONST_INT_P (h2) && INTVAL (h2) < 0 && SIGNED_INT12 (INTVAL (h2))) - { - emit_insn (gen_sub_f (l0, l1, gen_int_mode (-INTVAL (l2), SImode))); - emit_insn (gen_sbc (h0, h1, - gen_int_mode (-INTVAL (h2) - (l1 != 0), SImode), - cc_c)); - DONE; - } - emit_insn (gen_add_f (l0, l1, l2)); - emit_insn (gen_adc (h0, h1, h2)); - DONE; - } -}) +{}) ; This assumes that there can be no strictly partial overlap between ; operands[1] and operands[2]. @@ -2911,20 +2888,6 @@ { if (!register_operand (operands[2], DImode)) operands[1] = force_reg (DImode, operands[1]); - if (TARGET_EXPAND_ADDDI) - { - rtx l0 = gen_lowpart (SImode, operands[0]); - rtx h0 = disi_highpart (operands[0]); - rtx l1 = gen_lowpart (SImode, operands[1]); - rtx h1 = disi_highpart (operands[1]); - rtx l2 = gen_lowpart (SImode, operands[2]); - rtx h2 = disi_highpart (operands[2]); - rtx cc_c = gen_rtx_REG (CC_Cmode, CC_REG); - - emit_insn (gen_sub_f (l0, l1, l2)); - emit_insn (gen_sbc (h0, h1, h2, cc_c)); - DONE; - } }) (define_insn_and_split "subdi3_i" diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt index ed2b827..ad2df26 100644 --- a/gcc/config/arc/arc.opt +++ b/gcc/config/arc/arc.opt @@ -328,7 +328,7 @@ Target Var(TARGET_Q_CLASS) Enable 'q' instruction alternatives. mexpand-adddi -Target Var(TARGET_EXPAND_ADDDI) +Target Warn(%qs is deprecated) Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index b9d071b..dfde403 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -14906,7 +14906,7 @@ Enable pre-reload use of the @code{cbranchsi} pattern. @item -mexpand-adddi @opindex mexpand-adddi Expand @code{adddi3} and @code{subdi3} at RTL generation time into -@code{add.f}, @code{adc} etc. +@code{add.f}, @code{adc} etc. This option is deprecated. @item -mindexed-loads @opindex mindexed-loads |