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| author | James Greenhalgh <james.greenhalgh@arm.com> | 2017-08-31 16:03:09 +0000 |
|---|---|---|
| committer | James Greenhalgh <jgreenhalgh@gcc.gnu.org> | 2017-08-31 16:03:09 +0000 |
| commit | 3ec5b5f015903512558b480752056ac9e41e8f3d (patch) | |
| tree | 4b81afe9c0409697be8e864ed176820f5a074a50 /gcc | |
| parent | b54d4018b17c8e7be96cedd211e7c9dd5d1c3e43 (diff) | |
| download | gcc-3ec5b5f015903512558b480752056ac9e41e8f3d.zip gcc-3ec5b5f015903512558b480752056ac9e41e8f3d.tar.gz gcc-3ec5b5f015903512558b480752056ac9e41e8f3d.tar.bz2 | |
[AArch64 obvious] Fix register constraints for aarch64_ml[as]_elt_merge<mode>
The MLA by-element instructions have the same restriction as other by-element
instructions whereby the forms operating on vectors of 16-bit integer data
may only use registers v0-v15. We have an iterator for that, applied to the
other patterns generating this instruction, so use that.
gcc/
* config/aarch64/aarch64-simd.md (aarch64_mla_elt_merge<mode>): Fix
register constraint for by-element operand.
(aarch64_mls_elt_merge<mode>): Likewise.
From-SVN: r251568
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 4 |
2 files changed, 8 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cf1e005..1d3794c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-08-31 James Greenhalgh <james.greenhalgh@arm.com> + + * config/aarch64/aarch64-simd.md (aarch64_mla_elt_merge<mode>): Fix + register constraint for by-element operand. + (aarch64_mls_elt_merge<mode>): Likewise. + 2017-08-31 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.c (arc_can_follow_jump): Check for short diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index a94c6fd..8f045c21 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1072,7 +1072,7 @@ [(set (match_operand:VDQHS 0 "register_operand" "=w") (plus:VDQHS (mult:VDQHS (vec_duplicate:VDQHS - (match_operand:<VEL> 1 "register_operand" "w")) + (match_operand:<VEL> 1 "register_operand" "<h_con>")) (match_operand:VDQHS 2 "register_operand" "w")) (match_operand:VDQHS 3 "register_operand" "0")))] "TARGET_SIMD" @@ -1132,7 +1132,7 @@ (minus:VDQHS (match_operand:VDQHS 1 "register_operand" "0") (mult:VDQHS (vec_duplicate:VDQHS - (match_operand:<VEL> 2 "register_operand" "w")) + (match_operand:<VEL> 2 "register_operand" "<h_con>")) (match_operand:VDQHS 3 "register_operand" "w"))))] "TARGET_SIMD" "mls\t%0.<Vtype>, %3.<Vtype>, %2.<Vetype>[0]" |