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author | Sofiane Naci <sofiane.naci@arm.com> | 2013-06-17 16:14:06 +0000 |
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committer | Sofiane Naci <sofiane@gcc.gnu.org> | 2013-06-17 16:14:06 +0000 |
commit | 3d33d06bac26650aa94d6c9de46b7ee4965af8e5 (patch) | |
tree | 80e58bad19741579a9b238471aef8beac087465b /gcc | |
parent | ee03e71d472a3f73cbc1a132a284309f36565972 (diff) | |
download | gcc-3d33d06bac26650aa94d6c9de46b7ee4965af8e5.zip gcc-3d33d06bac26650aa94d6c9de46b7ee4965af8e5.tar.gz gcc-3d33d06bac26650aa94d6c9de46b7ee4965af8e5.tar.bz2 |
aarch64-simd.md (aarch64_dup_lane<mode>): Add r<-w alternative and update.
gcc/
* config/aarch64/aarch64-simd.md (aarch64_dup_lane<mode>): Add r<-w
alternative and update.
(aarch64_dup_lanedi): Delete.
* config/aarch64/arm_neon.h (vdup<bhsd>_lane_*): Update.
* config/aarch64/aarch64-simd-builtins.def: Update.
testsuite/
* gcc.target/aarch64/scalar_intrinsics.c: Update.
From-SVN: r200152
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 8 | ||||
-rw-r--r-- | gcc/config/aarch64/aarch64-simd-builtins.def | 2 | ||||
-rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 27 | ||||
-rw-r--r-- | gcc/config/aarch64/arm_neon.h | 16 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c | 10 |
6 files changed, 34 insertions, 33 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a58dd00..d9e6187 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2013-06-17 Sofiane Naci <sofiane.naci@arm.com> + + * config/aarch64/aarch64-simd.md (aarch64_dup_lane<mode>): Add r<-w + alternative and update. + (aarch64_dup_lanedi): Delete. + * config/aarch64/arm_neon.h (vdup<bhsd>_lane_*): Update. + * config/aarch64/aarch64-simd-builtins.def: Update. + 2013-06-17 Richard Biener <rguenther@suse.de> * lto-streamer.h (enum LTO_tags): Add LTO_tree_scc. diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 5134f96..4d9b966 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -64,7 +64,7 @@ BUILTIN_VQ (REINTERP, reinterpretv2df, 0) BUILTIN_VDQ_I (BINOP, dup_lane, 0) - BUILTIN_SDQ_I (BINOP, dup_lane, 0) + BUILTIN_VDQ_I (BINOP, dup_lane_scalar, 0) /* Implemented by aarch64_<sur>q<r>shl<mode>. */ BUILTIN_VSDQ_I (BINOP, sqshl, 0) BUILTIN_VSDQ_I (BINOP, uqshl, 0) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 02037f3..08826b5 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -357,29 +357,18 @@ (set_attr "simd_mode" "<MODE>")] ) -(define_insn "aarch64_dup_lane<mode>" - [(set (match_operand:ALLX 0 "register_operand" "=w") +(define_insn "aarch64_dup_lane_scalar<mode>" + [(set (match_operand:<VEL> 0 "register_operand" "=w, r") (vec_select:<VEL> - (match_operand:<VCON> 1 "register_operand" "w") - (parallel [(match_operand:SI 2 "immediate_operand" "i")]) + (match_operand:VDQ 1 "register_operand" "w, w") + (parallel [(match_operand:SI 2 "immediate_operand" "i, i")]) ))] "TARGET_SIMD" - "dup\\t%<v>0<Vmtype>, %1.<Vetype>[%2]" - [(set_attr "simd_type" "simd_dup") - (set_attr "simd_mode" "<MODE>")] -) - -(define_insn "aarch64_dup_lanedi" - [(set (match_operand:DI 0 "register_operand" "=w,r") - (vec_select:DI - (match_operand:V2DI 1 "register_operand" "w,w") - (parallel [(match_operand:SI 2 "immediate_operand" "i,i")])))] - "TARGET_SIMD" "@ - dup\\t%<v>0<Vmtype>, %1.<Vetype>[%2] - umov\t%0, %1.d[%2]" - [(set_attr "simd_type" "simd_dup") - (set_attr "simd_mode" "DI")] + dup\\t%<Vetype>0, %1.<Vetype>[%2] + umov\\t%<vw>0, %1.<Vetype>[%2]" + [(set_attr "simd_type" "simd_dup, simd_movgp") + (set_attr "simd_mode" "<MODE>")] ) (define_insn "aarch64_simd_dup<mode>" diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 608db35..760ba3d 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -20234,49 +20234,49 @@ vcvtpq_u64_f64 (float64x2_t __a) __extension__ static __inline int8x1_t __attribute__ ((__always_inline__)) vdupb_lane_s8 (int8x16_t a, int const b) { - return __builtin_aarch64_dup_laneqi (a, b); + return __builtin_aarch64_dup_lane_scalarv16qi (a, b); } __extension__ static __inline uint8x1_t __attribute__ ((__always_inline__)) vdupb_lane_u8 (uint8x16_t a, int const b) { - return (uint8x1_t) __builtin_aarch64_dup_laneqi ((int8x16_t) a, b); + return (uint8x1_t) __builtin_aarch64_dup_lane_scalarv16qi ((int8x16_t) a, b); } __extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) vduph_lane_s16 (int16x8_t a, int const b) { - return __builtin_aarch64_dup_lanehi (a, b); + return __builtin_aarch64_dup_lane_scalarv8hi (a, b); } __extension__ static __inline uint16x1_t __attribute__ ((__always_inline__)) vduph_lane_u16 (uint16x8_t a, int const b) { - return (uint16x1_t) __builtin_aarch64_dup_lanehi ((int16x8_t) a, b); + return (uint16x1_t) __builtin_aarch64_dup_lane_scalarv8hi ((int16x8_t) a, b); } __extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) vdups_lane_s32 (int32x4_t a, int const b) { - return __builtin_aarch64_dup_lanesi (a, b); + return __builtin_aarch64_dup_lane_scalarv4si (a, b); } __extension__ static __inline uint32x1_t __attribute__ ((__always_inline__)) vdups_lane_u32 (uint32x4_t a, int const b) { - return (uint32x1_t) __builtin_aarch64_dup_lanesi ((int32x4_t) a, b); + return (uint32x1_t) __builtin_aarch64_dup_lane_scalarv4si ((int32x4_t) a, b); } __extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) vdupd_lane_s64 (int64x2_t a, int const b) { - return __builtin_aarch64_dup_lanedi (a, b); + return __builtin_aarch64_dup_lane_scalarv2di (a, b); } __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vdupd_lane_u64 (uint64x2_t a, int const b) { - return (uint64x1_t) __builtin_aarch64_dup_lanedi ((int64x2_t) a, b); + return (uint64x1_t) __builtin_aarch64_dup_lane_scalarv2di ((int64x2_t) a, b); } /* vldn */ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 147ae19..cb05b1c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2013-06-17 Sofiane Naci <sofiane.naci@arm.com> + + * gcc.target/aarch64/scalar_intrinsics.c: Update. + 2013-06-17 Paolo Carlini <paolo.carlini@oracle.com> PR c++/16128 diff --git a/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c b/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c index 16537ce..46d3449 100644 --- a/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c +++ b/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -dp" } */ #include <arm_neon.h> @@ -181,7 +181,7 @@ test_vcltzd_s64 (int64x1_t a) return res; } -/* { dg-final { scan-assembler-times "\\tdup\\tb\[0-9\]+, v\[0-9\]+\.b" 2 } } */ +/* { dg-final { scan-assembler-times "aarch64_dup_lane_scalarv16qi" 2 } } */ int8x1_t test_vdupb_lane_s8 (int8x16_t a) @@ -195,7 +195,7 @@ test_vdupb_lane_u8 (uint8x16_t a) return vdupb_lane_u8 (a, 2); } -/* { dg-final { scan-assembler-times "\\tdup\\th\[0-9\]+, v\[0-9\]+\.h" 2 } } */ +/* { dg-final { scan-assembler-times "aarch64_dup_lane_scalarv8hi" 2 } } */ int16x1_t test_vduph_lane_s16 (int16x8_t a) @@ -209,7 +209,7 @@ test_vduph_lane_u16 (uint16x8_t a) return vduph_lane_u16 (a, 2); } -/* { dg-final { scan-assembler-times "\\tdup\\ts\[0-9\]+, v\[0-9\]+\.s" 2 } } */ +/* { dg-final { scan-assembler-times "aarch64_dup_lane_scalarv4si" 2 } } */ int32x1_t test_vdups_lane_s32 (int32x4_t a) @@ -223,7 +223,7 @@ test_vdups_lane_u32 (uint32x4_t a) return vdups_lane_u32 (a, 2); } -/* { dg-final { scan-assembler-times "\\tumov\\tx\[0-9\]+, v\[0-9\]+\.d" 2 } } */ +/* { dg-final { scan-assembler-times "aarch64_dup_lane_scalarv2di" 2 } } */ int64x1_t test_vdupd_lane_s64 (int64x2_t a) |