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authorUros Bizjak <uros@gcc.gnu.org>2008-03-10 14:33:07 +0100
committerUros Bizjak <uros@gcc.gnu.org>2008-03-10 14:33:07 +0100
commit3b509e336185d75d64ddba6e3866f1cfbc986111 (patch)
tree5de1395a8519747f4a32d5e94c95b0a800728632 /gcc
parent9886a872b9837fecf3806cad9bbc7b19a2ced32f (diff)
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* ChangeLog: Remove merge marker.
From-SVN: r133077
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog6
1 files changed, 2 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6e5619f..052d616 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -21,7 +21,7 @@
2008-03-09 Uros Bizjak <ubizjak@gmail.com>
PR target/35496
- * config/i386/i386.c (ix86_constant_algnment): Compute alignment using
+ * config/i386/i386.c (ix86_constant_alignment): Compute alignment using
ALIGN_MODE_128 for VECTOR_CST and INTEGER_CST in addition to REAL_CST.
2008-03-09 Ira Rosen <irar@il.ibm.com>
@@ -416,7 +416,6 @@
transformations for modes that have signed zeros.
* ifcvt.c (noce_try_abs): Ditto.
->>>>>>> .r132956
2008-03-04 Joseph Myers <joseph@codesourcery.com>
* config/i386/i386.c (override_options): Force
@@ -1772,8 +1771,7 @@
(OPTION_MASK_ISA_SSE5_UNSET): Likewise.
(OPTION_MASK_ISA_SSE4): Removed.
(ix86_handle_option): Turn on bits in ix86_isa_flags and
- ix86_isa_flags_explicit with OPTION_MASK_ISA_XXX_SET for
- -mXXX.
+ ix86_isa_flags_explicit with OPTION_MASK_ISA_XXX_SET for -mXXX.
(override_options): Don't turn on implied SSE/MMX bits in
ix86_isa_flags.