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| author | Pan Li <pan2.li@intel.com> | 2024-12-04 10:08:12 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2024-12-06 08:42:27 +0800 |
| commit | 3ac3093756cd00f50e63e8dcde4d278606722105 (patch) | |
| tree | 0655fb09a2aee12a8e74799c0accf2bb3c77b861 /gcc | |
| parent | b7baa22e47421d0a81202a333f43d88b5bbb39f5 (diff) | |
| download | gcc-3ac3093756cd00f50e63e8dcde4d278606722105.zip gcc-3ac3093756cd00f50e63e8dcde4d278606722105.tar.gz gcc-3ac3093756cd00f50e63e8dcde4d278606722105.tar.bz2 | |
RISC-V: Refactor the testcases for bswap16-0
This patch would like to refactor the testcases of bswap16-0
after sorts of optimization option passing to testcase. To
fits the big lmul like m8 for asm dump check.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/unop/bswap16-0.c: Update
the vector register RE to cover v10 - v31.
Signed-off-by: Pan Li <pan2.li@intel.com>
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c index 605b356..4b55c00 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c @@ -10,7 +10,7 @@ ** ... ** vsrl\.vi\s+v[0-9]+,\s*v[0-9],\s*8+ ** vsll\.vi\s+v[0-9]+,\s*v[0-9],\s*8+ -** vor\.vv\s+v[0-9]+,\s*v[0-9],\s*v[0-9]+ +** vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ TEST_UNARY_CALL (uint16_t, __builtin_bswap16) |