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author | Uros Bizjak <uros@gcc.gnu.org> | 2015-04-01 19:36:24 +0200 |
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committer | Uros Bizjak <uros@gcc.gnu.org> | 2015-04-01 19:36:24 +0200 |
commit | 35238bb505daa6a00cfaec9acdee2d1867788d53 (patch) | |
tree | 74f4612e2c9894fb6ae621deb44775d526db9c32 /gcc | |
parent | f87cb0b73403b26113c52b5efa70e93332053dfe (diff) | |
download | gcc-35238bb505daa6a00cfaec9acdee2d1867788d53.zip gcc-35238bb505daa6a00cfaec9acdee2d1867788d53.tar.gz gcc-35238bb505daa6a00cfaec9acdee2d1867788d53.tar.bz2 |
sync.md (UNSPEC_MOVA): Remove.
* config/i386/sync.md (UNSPEC_MOVA): Remove.
(atomic_load<mode>): Change operand 0 predicate to
nonimmediate_operand and fix up the destination when needed.
Use UNSPEC_LDA.
(atomic_loaddi_fpu): Use UNSPEC_LDA.
(atomic_store<mode>): Change operand 1 predicate to
nonimmendate_operand and move the source to register when needed.
Use UNSPEC_STA.
(atomic_store<mode>_1): Use UNSPEC_STA.
(atomic_storedi_fpu): Change operand 1 to nonimmediate_operand.
Fix moves from memory operand. Use UNSPEC_STA.
From-SVN: r221811
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 18 | ||||
-rw-r--r-- | gcc/config/i386/sync.md | 36 |
2 files changed, 41 insertions, 13 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 47c0f22..e2e8b55 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2015-04-01 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/sync.md (UNSPEC_MOVA): Remove. + (atomic_load<mode>): Change operand 0 predicate to + nonimmediate_operand and fix up the destination when needed. + Use UNSPEC_LDA. + (atomic_loaddi_fpu): Use UNSPEC_LDA. + (atomic_store<mode>): Change operand 1 predicate to + nonimmendate_operand and move the source to register when needed. + Use UNSPEC_STA. + (atomic_store<mode>_1): Use UNSPEC_STA. + (atomic_storedi_fpu): Change operand 1 to nonimmediate_operand. + Fix moves from memory operand. Use UNSPEC_STA. + 2015-04-01 Bernd Edlinger <bernd.edlinger@hotmail.de> * expmed.c (strict_volatile_bitfield_p): Check that the access will @@ -8,8 +22,8 @@ 2015-04-01 Max Ostapenko <m.ostapenko@partner.samsung.com> PR target/65624 - * config/aarch64/aarch64-builtins.c (aarch64_simd_expand_builtin): Increase - args array size by one to avoid buffer overflow. + * config/aarch64/aarch64-builtins.c (aarch64_simd_expand_builtin): + Increase args array size by one to avoid buffer overflow. 2015-03-31 Jan Hubicka <hubicka@ucw.cz> diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md index 28b8122..3ef580b 100644 --- a/gcc/config/i386/sync.md +++ b/gcc/config/i386/sync.md @@ -21,7 +21,8 @@ UNSPEC_LFENCE UNSPEC_SFENCE UNSPEC_MFENCE - UNSPEC_MOVA ; For __atomic support + + ;; __atomic support UNSPEC_LDA UNSPEC_STA ]) @@ -140,10 +141,10 @@ ]) (define_expand "atomic_load<mode>" - [(set (match_operand:ATOMIC 0 "register_operand") + [(set (match_operand:ATOMIC 0 "nonimmediate_operand") (unspec:ATOMIC [(match_operand:ATOMIC 1 "memory_operand") (match_operand:SI 2 "const_int_operand")] - UNSPEC_MOVA))] + UNSPEC_LDA))] "" { /* For DImode on 32-bit, we can use the FPU to perform the load. */ @@ -152,14 +153,25 @@ (operands[0], operands[1], assign_386_stack_local (DImode, SLOT_TEMP))); else - emit_move_insn (operands[0], operands[1]); + { + rtx dst = operands[0]; + + if (MEM_P (dst)) + dst = gen_reg_rtx (<MODE>mode); + + emit_move_insn (dst, operands[1]); + + /* Fix up the destination if needed. */ + if (dst != operands[0]) + emit_move_insn (operands[0], dst); + } DONE; }) (define_insn_and_split "atomic_loaddi_fpu" [(set (match_operand:DI 0 "nonimmediate_operand" "=x,m,?r") (unspec:DI [(match_operand:DI 1 "memory_operand" "m,m,m")] - UNSPEC_MOVA)) + UNSPEC_LDA)) (clobber (match_operand:DI 2 "memory_operand" "=X,X,m")) (clobber (match_scratch:DF 3 "=X,xf,xf"))] "!TARGET_64BIT && (TARGET_80387 || TARGET_SSE)" @@ -197,9 +209,9 @@ (define_expand "atomic_store<mode>" [(set (match_operand:ATOMIC 0 "memory_operand") - (unspec:ATOMIC [(match_operand:ATOMIC 1 "register_operand") + (unspec:ATOMIC [(match_operand:ATOMIC 1 "nonimmediate_operand") (match_operand:SI 2 "const_int_operand")] - UNSPEC_MOVA))] + UNSPEC_STA))] "" { enum memmodel model = (enum memmodel) (INTVAL (operands[2]) & MEMMODEL_MASK); @@ -215,6 +227,8 @@ } else { + operands[1] = force_reg (<MODE>mode, operands[1]); + /* For seq-cst stores, when we lack MFENCE, use XCHG. */ if (model == MEMMODEL_SEQ_CST && !(TARGET_64BIT || TARGET_SSE2)) { @@ -238,14 +252,14 @@ [(set (match_operand:SWI 0 "memory_operand" "=m") (unspec:SWI [(match_operand:SWI 1 "<nonmemory_operand>" "<r><i>") (match_operand:SI 2 "const_int_operand")] - UNSPEC_MOVA))] + UNSPEC_STA))] "" "%K2mov{<imodesuffix>}\t{%1, %0|%0, %1}") (define_insn_and_split "atomic_storedi_fpu" [(set (match_operand:DI 0 "memory_operand" "=m,m,m") - (unspec:DI [(match_operand:DI 1 "register_operand" "x,m,?r")] - UNSPEC_MOVA)) + (unspec:DI [(match_operand:DI 1 "nonimmediate_operand" "x,m,?r")] + UNSPEC_STA)) (clobber (match_operand:DI 2 "memory_operand" "=X,X,m")) (clobber (match_scratch:DF 3 "=X,xf,xf"))] "!TARGET_64BIT && (TARGET_80387 || TARGET_SSE)" @@ -273,7 +287,7 @@ else { adjust_reg_mode (tmp, DImode); - emit_move_insn (tmp, mem); + emit_move_insn (tmp, src); src = tmp; } } |