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| author | Kewen Lin <linkw@linux.ibm.com> | 2024-08-21 00:26:20 -0500 |
|---|---|---|
| committer | Kewen Lin <linkw@gcc.gnu.org> | 2024-08-21 00:26:20 -0500 |
| commit | 34292a1ae89a13baf974ff2ecb21dcf89aab4617 (patch) | |
| tree | d4e96175c8355c8ff6f05c4a14dc82484be84c5b /gcc | |
| parent | ae53e4b99eaad43424f2b0cc1bbabb3b454fb6d8 (diff) | |
| download | gcc-34292a1ae89a13baf974ff2ecb21dcf89aab4617.zip gcc-34292a1ae89a13baf974ff2ecb21dcf89aab4617.tar.gz gcc-34292a1ae89a13baf974ff2ecb21dcf89aab4617.tar.bz2 | |
rs6000: Remove "+" constraint modifier from *vsx_le_perm_store_* insns
Since *vsx_le_perm_store_* can be split into vector
permute and vector store, after reload_completed, we reuse
the operand 1 as the destination of vector permute, so we
set operand 1 with constraint modifier "+". But since
it's taken as pure input in DF and most passes as Richard
pointed out in [1], to ensure it's correct when operand 1
is still live, we actually restore the operand 1's value
after the store with vector permute, that is:
op1 = vector permute op1 (doubleword swapping)
op0 = op2
op1 = vector permute op1 (doubleword swapping)
, it means op1's value isn't changed by this insn.
So according to the comments from Richard and Segher in
that thread, this patch is to remove the "+" constraint
modifier of operand 1 from *vsx_le_perm_store_* insns.
[1] https://gcc.gnu.org/pipermail/gcc-patches/2024-August/660145.html
gcc/ChangeLog:
* config/rs6000/vsx.md (define_insn *vsx_le_perm_store_{<VSX_D:mode>,
<VSX_W:mode>,v8hi,v16qi,<VSX_LE_128:mode>}): Remove constraint modifier
"+" from operand 1.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/rs6000/vsx.md | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 89eaef1..b2fc39a 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -659,7 +659,7 @@ (define_insn "*vsx_le_perm_store_<mode>" [(set (match_operand:VSX_D 0 "indexed_or_indirect_operand" "=Z") - (match_operand:VSX_D 1 "vsx_register_operand" "+wa"))] + (match_operand:VSX_D 1 "vsx_register_operand" "wa"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" [(set_attr "type" "vecstore") @@ -729,7 +729,7 @@ (define_insn "*vsx_le_perm_store_<mode>" [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand" "=Z") - (match_operand:VSX_W 1 "vsx_register_operand" "+wa"))] + (match_operand:VSX_W 1 "vsx_register_operand" "wa"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" [(set_attr "type" "vecstore") @@ -804,7 +804,7 @@ (define_insn "*vsx_le_perm_store_v8hi" [(set (match_operand:V8HI 0 "indexed_or_indirect_operand" "=Z") - (match_operand:V8HI 1 "vsx_register_operand" "+wa"))] + (match_operand:V8HI 1 "vsx_register_operand" "wa"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" [(set_attr "type" "vecstore") @@ -889,7 +889,7 @@ (define_insn "*vsx_le_perm_store_v16qi" [(set (match_operand:V16QI 0 "indexed_or_indirect_operand" "=Z") - (match_operand:V16QI 1 "vsx_register_operand" "+wa"))] + (match_operand:V16QI 1 "vsx_register_operand" "wa"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" [(set_attr "type" "vecstore") @@ -1059,7 +1059,7 @@ (define_insn "*vsx_le_perm_store_<mode>" [(set (match_operand:VSX_LE_128 0 "memory_operand" "=Z,Q") - (match_operand:VSX_LE_128 1 "vsx_register_operand" "+wa,r"))] + (match_operand:VSX_LE_128 1 "vsx_register_operand" "wa,r"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !altivec_indexed_or_indirect_operand (operands[0], <MODE>mode)" "@ |