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| author | Eric Botcazou <ebotcazou@gcc.gnu.org> | 2012-02-12 20:42:45 +0000 |
|---|---|---|
| committer | Eric Botcazou <ebotcazou@gcc.gnu.org> | 2012-02-12 20:42:45 +0000 |
| commit | 31d7b43969c67db9d412d9a99c153133779e83b8 (patch) | |
| tree | b6e98596702f84d6a818be2ba0f27dad4e1dc318 /gcc | |
| parent | 5b4a7d0d8a03c4d3313565e71f77b97ea208e517 (diff) | |
| download | gcc-31d7b43969c67db9d412d9a99c153133779e83b8.zip gcc-31d7b43969c67db9d412d9a99c153133779e83b8.tar.gz gcc-31d7b43969c67db9d412d9a99c153133779e83b8.tar.bz2 | |
sparc.h (CANNOT_CHANGE_MODE_CLASS): In 64-bit mode, disallow changes from SFmode to mode with different size in FP regs.
* config/sparc/sparc.h (CANNOT_CHANGE_MODE_CLASS): In 64-bit mode,
disallow changes from SFmode to mode with different size in FP regs.
From-SVN: r184144
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc.h | 11 |
2 files changed, 13 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 44b8b88..1a97108 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,4 +1,9 @@ -2012-01-29 Robert Millan <rmh@gnu.org> +2012-02-12 Eric Botcazou <ebotcazou@adacore.com> + + * config/sparc/sparc.h (CANNOT_CHANGE_MODE_CLASS): In 64-bit mode, + disallow changes from SFmode to mode with different size in FP regs. + +2012-02-12 Robert Millan <rmh@gnu.org> Gerald Pfeifer <gerald@pfeifer.com> * ginclude/stddef.h [__FreeBSD_kernel__] (__size_t): Do not define. diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index bb6b079..acc6be1 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -894,18 +894,21 @@ extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] -/* Defines invalid mode changes. Borrowed from pa64-regs.h. +/* Defines invalid mode changes. Borrowed from the PA port. SImode loads to floating-point registers are not zero-extended. The definition for LOAD_EXTEND_OP specifies that integer loads narrower than BITS_PER_WORD will be zero-extended. As a result, we inhibit changes from SImode unless they are to a mode that is - identical in size. */ + identical in size. + + Likewise for SFmode, since word-mode paradoxical subregs are + problematic on big-endian architectures. */ #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ (TARGET_ARCH64 \ - && (FROM) == SImode \ - && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ + && GET_MODE_SIZE (FROM) == 4 \ + && GET_MODE_SIZE (TO) != 4 \ ? reg_classes_intersect_p (CLASS, FP_REGS) : 0) /* This is the order in which to allocate registers normally. |