diff options
author | Xi Ruoyao <xry111@xry111.site> | 2023-12-17 04:26:23 +0800 |
---|---|---|
committer | Xi Ruoyao <xry111@xry111.site> | 2023-12-23 20:58:34 +0800 |
commit | 310dc75e7004d8b8e39c6f258b28b2165ad4193c (patch) | |
tree | f21f53aee3ff759c9958dfde0ace6bbc310ece00 /gcc | |
parent | 78607d122976cbfd39b0b12e9be662c47c81fed0 (diff) | |
download | gcc-310dc75e7004d8b8e39c6f258b28b2165ad4193c.zip gcc-310dc75e7004d8b8e39c6f258b28b2165ad4193c.tar.gz gcc-310dc75e7004d8b8e39c6f258b28b2165ad4193c.tar.bz2 |
LoongArch: Add sign_extend pattern for 32-bit rotate shift
Remove a redundant sign extension.
gcc/ChangeLog:
* config/loongarch/loongarch.md (rotrsi3_extend): New
define_insn.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/rotrw.c: New test.
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/config/loongarch/loongarch.md | 10 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/loongarch/rotrw.c | 17 |
2 files changed, 27 insertions, 0 deletions
diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index b48e8b5..7021105 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -2893,6 +2893,16 @@ [(set_attr "type" "shift,shift") (set_attr "mode" "<MODE>")]) +(define_insn "rotrsi3_extend" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (sign_extend:DI + (rotatert:SI (match_operand:SI 1 "register_operand" "r,r") + (match_operand:SI 2 "arith_operand" "r,I"))))] + "TARGET_64BIT" + "rotr%i2.w\t%0,%1,%2" + [(set_attr "type" "shift,shift") + (set_attr "mode" "SI")]) + ;; The following templates were added to generate "bstrpick.d + alsl.d" ;; instruction pairs. ;; It is required that the values of const_immalsl_operand and diff --git a/gcc/testsuite/gcc.target/loongarch/rotrw.c b/gcc/testsuite/gcc.target/loongarch/rotrw.c new file mode 100644 index 0000000..6ed45e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/rotrw.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler "rotr\\.w\t\\\$r4,\\\$r4,\\\$r5" } } */ +/* { dg-final { scan-assembler "rotri\\.w\t\\\$r4,\\\$r4,5" } } */ +/* { dg-final { scan-assembler-not "slli\\.w" } } */ + +unsigned +rotr (unsigned a, unsigned b) +{ + return a >> b | a << 32 - b; +} + +unsigned +rotri (unsigned a) +{ + return a >> 5 | a << 27; +} |