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author | Jonathan Wright <jonathan.wright@arm.com> | 2021-01-27 17:25:18 +0000 |
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committer | Jonathan Wright <jonathan.wright@arm.com> | 2021-02-03 13:35:24 +0000 |
commit | 2dac6586004a5b9d0baa07dd3c7f69d3e0fc4109 (patch) | |
tree | b82e6ef975d9deb87d6293e589ac1cb0418f4d1d /gcc | |
parent | 719877b079678f68f8acb3b4202432e93cd2c5a0 (diff) | |
download | gcc-2dac6586004a5b9d0baa07dd3c7f69d3e0fc4109.zip gcc-2dac6586004a5b9d0baa07dd3c7f69d3e0fc4109.tar.gz gcc-2dac6586004a5b9d0baa07dd3c7f69d3e0fc4109.tar.bz2 |
aarch64: Use RTL builtins for [su]mlal_high_n intrinsics
Rewrite [su]mlal_high_n Neon intrinsics to use RTL builtins rather
than inline assembly code, allowing for better scheduling and
optimization.
gcc/ChangeLog:
2021-01-27 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Add [su]mlal_hi_n
builtin generator macros.
* config/aarch64/aarch64-simd.md (aarch64_<su>mlal_hi_n<mode>_insn):
Define.
(aarch64_<su>mlal_hi_n<mode>): Define.
* config/aarch64/arm_neon.h (vmlal_high_n_s16): Use RTL builtin
instead of inline asm.
(vmlal_high_n_s32): Likewise.
(vmlal_high_n_u16): Likewise.
(vmlal_high_n_u32): Likewise.
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/config/aarch64/aarch64-simd-builtins.def | 4 | ||||
-rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 29 | ||||
-rw-r--r-- | gcc/config/aarch64/arm_neon.h | 28 |
3 files changed, 37 insertions, 24 deletions
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 8cf5737..352a99c 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -244,6 +244,10 @@ BUILTIN_VQW (TERNOP, smlal_hi, 0, NONE) BUILTIN_VQW (TERNOPU, umlal_hi, 0, NONE) + /* Implemented by aarch64_<su>mlal_hi_n<mode>. */ + BUILTIN_VQ_HSI (TERNOP, smlal_hi_n, 0, NONE) + BUILTIN_VQ_HSI (TERNOPU, umlal_hi_n, 0, NONE) + BUILTIN_VSQN_HSDI (UNOPUS, sqmovun, 0, NONE) /* Implemented by aarch64_sqxtun2<mode>. */ diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index d10cc2a..e76c71e 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -2006,6 +2006,35 @@ } ) +(define_insn "aarch64_<su>mlal_hi_n<mode>_insn" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (plus:<VWIDE> + (mult:<VWIDE> + (ANY_EXTEND:<VWIDE> (vec_select:<VHALF> + (match_operand:VQ_HSI 2 "register_operand" "w") + (match_operand:VQ_HSI 3 "vect_par_cnst_hi_half" ""))) + (ANY_EXTEND:<VWIDE> (vec_duplicate:<VCOND> + (match_operand:<VEL> 4 "register_operand" "<h_con>")))) + (match_operand:<VWIDE> 1 "register_operand" "0")))] + "TARGET_SIMD" + "<su>mlal2\t%0.<Vwtype>, %2.<Vtype>, %4.<Vetype>[0]" + [(set_attr "type" "neon_mla_<Vetype>_long")] +) + +(define_expand "aarch64_<su>mlal_hi_n<mode>" + [(match_operand:<VWIDE> 0 "register_operand") + (match_operand:<VWIDE> 1 "register_operand") + (ANY_EXTEND:<VWIDE>(match_operand:VQ_HSI 2 "register_operand")) + (match_operand:<VEL> 3 "register_operand")] + "TARGET_SIMD" +{ + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); + emit_insn (gen_aarch64_<su>mlal_hi_n<mode>_insn (operands[0], + operands[1], operands[2], p, operands[3])); + DONE; +} +) + (define_insn "*aarch64_<su>mlsl_lo<mode>" [(set (match_operand:<VWIDE> 0 "register_operand" "=w") (minus:<VWIDE> diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index e994aa1..e1f9c53 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -7268,48 +7268,28 @@ __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_high_n_s16 (int32x4_t __a, int16x8_t __b, int16_t __c) { - int32x4_t __result; - __asm__ ("smlal2 %0.4s,%2.8h,%3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlal_hi_nv8hi (__a, __b, __c); } __extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_high_n_s32 (int64x2_t __a, int32x4_t __b, int32_t __c) { - int64x2_t __result; - __asm__ ("smlal2 %0.2d,%2.4s,%3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlal_hi_nv4si (__a, __b, __c); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_high_n_u16 (uint32x4_t __a, uint16x8_t __b, uint16_t __c) { - uint32x4_t __result; - __asm__ ("umlal2 %0.4s,%2.8h,%3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlal_hi_nv8hi_uuuu (__a, __b, __c); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_high_n_u32 (uint64x2_t __a, uint32x4_t __b, uint32_t __c) { - uint64x2_t __result; - __asm__ ("umlal2 %0.2d,%2.4s,%3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlal_hi_nv4si_uuuu (__a, __b, __c); } __extension__ extern __inline int16x8_t |