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| author | Andrea Corallo <andrea.corallo@arm.com> | 2020-11-05 08:57:03 +0000 |
|---|---|---|
| committer | Andrea Corallo <andrea.corallo@arm.com> | 2020-11-09 12:35:18 +0100 |
| commit | 2d4fa1f79c7b7a01e0b4fa27ee37b7030e6bf93f (patch) | |
| tree | 07c5972122877cddf5c171567517a098ccc90f01 /gcc | |
| parent | dc7e8839c92c4bc3c3741cf27b0af81edb803fe7 (diff) | |
| download | gcc-2d4fa1f79c7b7a01e0b4fa27ee37b7030e6bf93f.zip gcc-2d4fa1f79c7b7a01e0b4fa27ee37b7030e6bf93f.tar.gz gcc-2d4fa1f79c7b7a01e0b4fa27ee37b7030e6bf93f.tar.bz2 | |
arm: [testcase] Better narrow some bfloat16 testcase
2020-11-05 Andrea Corallo <andrea.corallo@arm.com>
* gcc.target/arm/simd/vld1_lane_bf16_1.c: Require target to
support and add -mfloat-abi=hard flag.
* gcc.target/arm/simd/vld1_lane_bf16_indices_1.c: Likewise.
* gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c: Likewise.
* gcc.target/arm/simd/vst1_lane_bf16_1.c: Likewise.
* gcc.target/arm/simd/vst1_lane_bf16_indices_1.c: Likewise.
* gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c: Likewise.
Diffstat (limited to 'gcc')
6 files changed, 12 insertions, 2 deletions
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c index fa4e45b..94fb38f 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c @@ -1,7 +1,8 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-add-options arm_v8_2a_bf16_neon } */ -/* { dg-additional-options "-O3 --save-temps" } */ +/* { dg-additional-options "-O3 --save-temps -mfloat-abi=hard" } */ #include "arm_neon.h" diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c index c83eb53..d9af512 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-add-options arm_v8_2a_bf16_neon } */ +/* { dg-additional-options "-mfloat-abi=hard" } */ #include "arm_neon.h" diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c index 8e21e61..a73184c 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-add-options arm_v8_2a_bf16_neon } */ +/* { dg-additional-options "-mfloat-abi=hard" } */ #include "arm_neon.h" diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c index e018ec6..8564b8f 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c @@ -1,7 +1,8 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-add-options arm_v8_2a_bf16_neon } */ -/* { dg-additional-options "-O3 --save-temps" } */ +/* { dg-additional-options "-O3 --save-temps -mfloat-abi=hard" } */ #include "arm_neon.h" diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c index 39870dc..1bd6871 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-add-options arm_v8_2a_bf16_neon } */ +/* { dg-additional-options "-mfloat-abi=hard" } */ #include "arm_neon.h" diff --git a/gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c b/gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c index f31bd12..f18a479 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-add-options arm_v8_2a_bf16_neon } */ +/* { dg-additional-options "-mfloat-abi=hard" } */ #include "arm_neon.h" |