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| author | Tamar Christina <tamar.christina@arm.com> | 2021-10-25 15:14:04 +0100 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2021-10-25 15:14:04 +0100 |
| commit | 2cbfaba60661ebbdfcffe725ab55fbb323e2a187 (patch) | |
| tree | b70bb8900c7efaf39e948a1b8a0de1ea7124d06f /gcc | |
| parent | f217e87972a2a207e793101fc05cfc9dd095c678 (diff) | |
| download | gcc-2cbfaba60661ebbdfcffe725ab55fbb323e2a187.zip gcc-2cbfaba60661ebbdfcffe725ab55fbb323e2a187.tar.gz gcc-2cbfaba60661ebbdfcffe725ab55fbb323e2a187.tar.bz2 | |
AArch64 testsuite: Force shrn-combine-*.c to use NEON.
These tests are testing Advanced SIMD codegen, so if the compiler or the
testsuite is forcing SVE they will fail.
This adds +nosve so that we always generate Advanced SIMD codegen.
gcc/testsuite/ChangeLog:
PR target/102907
* gcc.target/aarch64/shrn-combine-1.c: Disable SVE.
* gcc.target/aarch64/shrn-combine-2.c: Likewise.
* gcc.target/aarch64/shrn-combine-3.c: Likewise.
* gcc.target/aarch64/shrn-combine-4.c: Likewise.
* gcc.target/aarch64/shrn-combine-5.c: Likewise.
* gcc.target/aarch64/shrn-combine-6.c: Likewise.
* gcc.target/aarch64/shrn-combine-7.c: Likewise.
Diffstat (limited to 'gcc')
7 files changed, 14 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-1.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-1.c index a285246..334e94a 100644 --- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-1.c +++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-1.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define TYPE char void foo (unsigned TYPE * restrict a, TYPE * restrict d, int n) diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-2.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-2.c index 012135b..c90de72 100644 --- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-2.c +++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-2.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define TYPE short void foo (unsigned TYPE * restrict a, TYPE * restrict d, int n) diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-3.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-3.c index 8b5b360..a05ecbb 100644 --- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-3.c +++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-3.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define TYPE int void foo (unsigned long long * restrict a, TYPE * restrict d, int n) diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-4.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-4.c index fedca76..36ebab7 100644 --- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-4.c +++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-4.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define TYPE long long void foo (unsigned TYPE * restrict a, TYPE * restrict d, int n) diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-5.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-5.c index 408e8553..973e577 100644 --- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-5.c +++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-5.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define TYPE1 char #define TYPE2 short #define SHIFT 8 diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-6.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-6.c index 6211ba3..db36a9c 100644 --- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-6.c +++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-6.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define TYPE1 short #define TYPE2 int #define SHIFT 16 diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-7.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-7.c index 56cbeac..e7caf3c 100644 --- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-7.c +++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-7.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define TYPE1 int #define TYPE2 long long #define SHIFT 32 |