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authorJeff Law <jlaw@ventanamicro.com>2025-09-07 12:11:55 -0600
committerJeff Law <jlaw@ventanamicro.com>2025-09-07 12:11:55 -0600
commit2b7afb69ab42367cd926bffb26ba713e51b91914 (patch)
treeb3e77c93f51862a58b90d6ba9ec824f48305815f /gcc
parent35cf8d85841a6301eeb12668085e326ddd115f6e (diff)
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[RISC-V] Fix ordering of pipeline models
I missed that the new ascalon pipeline description was put into the wrong place during review. The net is tests which wanted to use generic-ooo explicitly for stability in the test output ended up getting a different pipeline model and different codegen than the test expected. This tripped a small number of vsetvl failures in the testsuite. This has spun on riscv64-elf and riscv32-elf in my tester and fixes the regression. I'm going to go ahead and push it as I'm likely offline this afternoon/evening and don't want anyone else to waste their time chasing the regression down. gcc/ * config/riscv/riscv-opts.h (riscv_microarchitecture_type): Fix ordering.
Diffstat (limited to 'gcc')
-rw-r--r--gcc/config/riscv/riscv-opts.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 54f8978..4e4e9d8 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -57,10 +57,10 @@ enum riscv_microarchitecture_type {
sifive_7,
sifive_p400,
sifive_p600,
- tt_ascalon_d8,
xiangshan,
generic_ooo,
mips_p8700,
+ tt_ascalon_d8,
};
extern enum riscv_microarchitecture_type riscv_microarchitecture;