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| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2014-09-10 21:13:37 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2014-09-10 21:13:37 +0000 |
| commit | 29aafbc413cdc48e39bebf0f7a5b34e83ad67132 (patch) | |
| tree | 067850fe2ab7a624a18c13652f8a1ff2d4abc5e7 /gcc | |
| parent | 971ea67cc0cb151f951a4b17e48b1cb0b31523f2 (diff) | |
| download | gcc-29aafbc413cdc48e39bebf0f7a5b34e83ad67132.zip gcc-29aafbc413cdc48e39bebf0f7a5b34e83ad67132.tar.gz gcc-29aafbc413cdc48e39bebf0f7a5b34e83ad67132.tar.bz2 | |
vsx.md (vsx_fmav4sf4): Use correct constraints for V2DF, V4SF, DF, and DI modes.
2014-09-10 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/vsx.md (vsx_fmav4sf4): Use correct constraints for
V2DF, V4SF, DF, and DI modes.
(vsx_fmav2df2): Likewise.
(vsx_float_fix_<mode>2): Likewise.
(vsx_reduc_<VEC_reduc_name>_v2df_scalar): Likewise.
From-SVN: r215138
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/rs6000/vsx.md | 22 |
2 files changed, 19 insertions, 11 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6e532f8..a44c60d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2014-09-10 Michael Meissner <meissner@linux.vnet.ibm.com> + + * config/rs6000/vsx.md (vsx_fmav4sf4): Use correct constraints for + V2DF, V4SF, DF, and DI modes. + (vsx_fmav2df2): Likewise. + (vsx_float_fix_<mode>2): Likewise. + (vsx_reduc_<VEC_reduc_name>_v2df_scalar): Likewise. + 2014-09-10 Xinliang David Li <davidxl@google.com> PR target/63209 diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index dc78a61..7aa0f12 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -996,11 +996,11 @@ ;; multiply. (define_insn "*vsx_fmav4sf4" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,v") + [(set (match_operand:V4SF 0 "vsx_register_operand" "=wf,wf,?wa,?wa,v") (fma:V4SF - (match_operand:V4SF 1 "vsx_register_operand" "%ws,ws,wa,wa,v") - (match_operand:V4SF 2 "vsx_register_operand" "ws,0,wa,0,v") - (match_operand:V4SF 3 "vsx_register_operand" "0,ws,0,wa,v")))] + (match_operand:V4SF 1 "vsx_register_operand" "%wf,wf,wa,wa,v") + (match_operand:V4SF 2 "vsx_register_operand" "wf,0,wa,0,v") + (match_operand:V4SF 3 "vsx_register_operand" "0,wf,0,wa,v")))] "VECTOR_UNIT_VSX_P (V4SFmode)" "@ xvmaddasp %x0,%x1,%x2 @@ -1011,11 +1011,11 @@ [(set_attr "type" "vecfloat")]) (define_insn "*vsx_fmav2df4" - [(set (match_operand:V2DF 0 "vsx_register_operand" "=ws,ws,?wa,?wa") + [(set (match_operand:V2DF 0 "vsx_register_operand" "=wd,wd,?wa,?wa") (fma:V2DF - (match_operand:V2DF 1 "vsx_register_operand" "%ws,ws,wa,wa") - (match_operand:V2DF 2 "vsx_register_operand" "ws,0,wa,0") - (match_operand:V2DF 3 "vsx_register_operand" "0,ws,0,wa")))] + (match_operand:V2DF 1 "vsx_register_operand" "%wd,wd,wa,wa") + (match_operand:V2DF 2 "vsx_register_operand" "wd,0,wa,0") + (match_operand:V2DF 3 "vsx_register_operand" "0,wd,0,wa")))] "VECTOR_UNIT_VSX_P (V2DFmode)" "@ xvmaddadp %x0,%x1,%x2 @@ -1547,8 +1547,8 @@ (define_insn "vsx_concat_<mode>" [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSr>,?<VSa>") (vec_concat:VSX_D - (match_operand:<VS_scalar> 1 "vsx_register_operand" "ws,<VSa>") - (match_operand:<VS_scalar> 2 "vsx_register_operand" "ws,<VSa>")))] + (match_operand:<VS_scalar> 1 "vsx_register_operand" "<VS_64reg>,<VSa>") + (match_operand:<VS_scalar> 2 "vsx_register_operand" "<VS_64reg>,<VSa>")))] "VECTOR_MEM_VSX_P (<MODE>mode)" { if (BYTES_BIG_ENDIAN) @@ -2221,7 +2221,7 @@ ;; to the top element of the V2DF array without doing an extract. (define_insn_and_split "*vsx_reduc_<VEC_reduc_name>_v2df_scalar" - [(set (match_operand:DF 0 "vfloat_operand" "=&ws,&?wa,ws,?wa") + [(set (match_operand:DF 0 "vfloat_operand" "=&ws,&?ws,ws,?ws") (vec_select:DF (VEC_reduc:V2DF (vec_concat:V2DF |