diff options
| author | Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | 2014-06-02 08:22:30 +0000 |
|---|---|---|
| committer | Ramana Radhakrishnan <ramana@gcc.gnu.org> | 2014-06-02 08:22:30 +0000 |
| commit | 27e83a44d3e372702614769190cab3f2d8575713 (patch) | |
| tree | 1f78941b652011d30f8727ef2a79c198824c3052 /gcc | |
| parent | 2ba0071e3da6e8f12e6e323e16de707211071e85 (diff) | |
| download | gcc-27e83a44d3e372702614769190cab3f2d8575713.zip gcc-27e83a44d3e372702614769190cab3f2d8575713.tar.gz gcc-27e83a44d3e372702614769190cab3f2d8575713.tar.bz2 | |
re PR target/61154 ([ARM] wide-int merge introduced regressions in vshuf tests)
Fix PR target/61154
2014-06-02 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
PR target/61154
* config/arm/arm.h (TARGET_SUPPORTS_WIDE_INT): Define.
* config/arm/arm.md (mov64 splitter): Replace const_double_operand
with immediate_operand.
From-SVN: r211129
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/arm/arm.h | 2 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 2 |
3 files changed, 9 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7e524c6..2efa59f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2014-06-02 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + + PR target/61154 + * config/arm/arm.h (TARGET_SUPPORTS_WIDE_INT): Define. + * config/arm/arm.md (mov64 splitter): Replace const_double_operand + with immediate_operand. + 2014-06-02 Andreas Schwab <schwab@suse.de> * config/ia64/ia64.c diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 1a35625..c325026 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2395,5 +2395,5 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); #endif #define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS - +#define TARGET_SUPPORTS_WIDE_INT 1 #endif /* ! GCC_ARM_H */ diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 75d0541..bec889a 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -5990,7 +5990,7 @@ (define_split [(set (match_operand:ANY64 0 "arm_general_register_operand" "") - (match_operand:ANY64 1 "const_double_operand" ""))] + (match_operand:ANY64 1 "immediate_operand" ""))] "TARGET_32BIT && reload_completed && (arm_const_double_inline_cost (operands[1]) |