diff options
author | Uros Bizjak <uros@gcc.gnu.org> | 2010-04-10 19:20:47 +0200 |
---|---|---|
committer | Uros Bizjak <uros@gcc.gnu.org> | 2010-04-10 19:20:47 +0200 |
commit | 27431d88dd1a06237f8a62a48f8bdd72154134d6 (patch) | |
tree | 172938f1757a12ff2723501c40af178899a9d293 /gcc | |
parent | a6d57223b149b3859ad5d5341a721a05b2e0060d (diff) | |
download | gcc-27431d88dd1a06237f8a62a48f8bdd72154134d6.zip gcc-27431d88dd1a06237f8a62a48f8bdd72154134d6.tar.gz gcc-27431d88dd1a06237f8a62a48f8bdd72154134d6.tar.bz2 |
i386.md (ashr<mode>3): Macroize expander from ashr{qi,hi,si,di,ti}3_1 using SDWIM mode iterator.
* config/i386/i386.md (ashr<mode>3): Macroize expander from
ashr{qi,hi,si,di,ti}3_1 using SDWIM mode iterator.
(*ashr<mode>3_doubleword): New insn_and_split_pattern. Macroize
pattern from *ashr{di,ti}3_1 and corresponding splitters using
DWI mode iterator.
(*ashr<mode>3_doubleword peephole2): Macroize peephole2 pattern
from corresponding peephole2 patterns.
(ashrdi3_cvt): Rename from ashrdi3_63_rex64.
(ashrsi3_cvt): Rename from ashrsi3_31.
(*ashrsi3_cvt_zext): Rename from *ashrsi3_31_zext.
(x86_shift<mode>_adj_3): Macroize expander from x86_shift_adj_3
and x86_64_shift_adj_3 using SWI48 mode iterator.
(*ashr<mode>3_1): Merge with *ashr{qi,hi,si}3_1_one_bit and
*ashrdi3_1_one_bit_rex64. Macroize insn from *ashr{qi,hi,si}3_cmp
and *ashrdi3_cmp_rex64 using SWI mode iterator.
(*ashrqi3_1_slp): Merge with *ashrqi3_1_one_bit_slp.
(*ashr<mode>3_cmp): Merge with *ashr{qi,hi,si}3_one_bit_cmp and
*ashrdi3_one_bit_cmp_rex64. Macroize insn from *ashr{qi,hi,si}3_cmp
and *ashrdi3_cmp_rex64 using SWI mode iterator.
(*ashrsi3_cmp_zext): Merge with *ashrsi3_cmp_one_bit_zext.
(*ashr<mode>3_cconly): Merge with *ashr{qi,hi,si}3_one_bit_cconly and
*ashrdi3_one_bit_cconly_rex64. Macroize insn from
*ashr{qi,hi,si}3_cconly and *ashrdi3_cconly_rex64 using
SWI mode iterator.
(sign_extend splitters): Update for renamed ashr{di,si}3_patterns.
* config/i386/i386.c (ix86_split_ashr): Update for renamed
x86_shift<mode>_adj_3 expander.
From-SVN: r158195
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 40 | ||||
-rw-r--r-- | gcc/config/i386/i386.c | 4 | ||||
-rw-r--r-- | gcc/config/i386/i386.md | 801 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 21 |
4 files changed, 262 insertions, 604 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 68bc18a..c053f3d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,33 @@ +2010-04-10 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/i386.md (ashr<mode>3): Macroize expander from + ashr{qi,hi,si,di,ti}3_1 using SDWIM mode iterator. + (*ashr<mode>3_doubleword): New insn_and_split_pattern. Macroize + pattern from *ashr{di,ti}3_1 and corresponding splitters using + DWI mode iterator. + (*ashr<mode>3_doubleword peephole2): Macroize peephole2 pattern + from corresponding peephole2 patterns. + (ashrdi3_cvt): Rename from ashrdi3_63_rex64. + (ashrsi3_cvt): Rename from ashrsi3_31. + (*ashrsi3_cvt_zext): Rename from *ashrsi3_31_zext. + (x86_shift<mode>_adj_3): Macroize expander from x86_shift_adj_3 + and x86_64_shift_adj_3 using SWI48 mode iterator. + (*ashr<mode>3_1): Merge with *ashr{qi,hi,si}3_1_one_bit and + *ashrdi3_1_one_bit_rex64. Macroize insn from *ashr{qi,hi,si}3_cmp + and *ashrdi3_cmp_rex64 using SWI mode iterator. + (*ashrqi3_1_slp): Merge with *ashrqi3_1_one_bit_slp. + (*ashr<mode>3_cmp): Merge with *ashr{qi,hi,si}3_one_bit_cmp and + *ashrdi3_one_bit_cmp_rex64. Macroize insn from *ashr{qi,hi,si}3_cmp + and *ashrdi3_cmp_rex64 using SWI mode iterator. + (*ashrsi3_cmp_zext): Merge with *ashrsi3_cmp_one_bit_zext. + (*ashr<mode>3_cconly): Merge with *ashr{qi,hi,si}3_one_bit_cconly and + *ashrdi3_one_bit_cconly_rex64. Macroize insn from + *ashr{qi,hi,si}3_cconly and *ashrdi3_cconly_rex64 using + SWI mode iterator. + (sign_extend splitters): Update for renamed ashr{di,si}3_patterns. + * config/i386/i386.c (ix86_split_ashr): Update for renamed + x86_shift<mode>_adj_3 expander. + 2010-04-10 Wei Guozhi <carrot@google.com> PR target/42601 @@ -44,8 +74,8 @@ 2010-04-09 Hariharan Sandanagobalane <hariharan@picochip.com> - * config/picochip/picochip.c (picochip_rtx_costs): Use correct function - template. + * config/picochip/picochip.c (picochip_rtx_costs): Use correct + function template. (picochip_override_options): Enable section anchors only above -O1. (picochip_reorg): Fixed a couple of build warnings. @@ -210,7 +240,7 @@ (ix86_attribute_table): Add description for thiscall attribute. * config/i386/i386.h (ix86_args): Adjust comment for member fastcall. * doc/extend.texi: Add documentation for thiscall. - + 2010-04-09 Manuel López-Ibáñez <manu@gcc.gnu.org> PR c++/28584 @@ -255,7 +285,7 @@ * gcc.h (DEFAULT_SWITCH_TAKES_ARG): Delete -b and -V. 2010-04-08 Christian Borntraeger <borntraeger@de.ibm.com> - Wolfgang Gellerich <gellerich@de.ibm.com> + Wolfgang Gellerich <gellerich@de.ibm.com> Implement target hook for loop unrolling * target.h (loop_unroll_adjust): Add a new target hook function. @@ -422,7 +452,7 @@ inserting GIMPLE_NOPs into the IL. * tree-ssa-structalias.c (get_constraint_for_component_ref): Explicitly strip handled components and indirect references. - + * fold-const.c (fold_unary_loc): Do not strip qualifiers when folding address expressions. * gimple.c (gimple_ior_addresses_taken_1): Use get_base_address. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 6431d9b..2c6a09c 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -17224,8 +17224,8 @@ ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode) } else emit_insn ((mode == DImode - ? gen_x86_shift_adj_3 - : gen_x86_64_shift_adj_3) (low[0], high[0], operands[2])); + ? gen_x86_shiftsi_adj_3 + : gen_x86_shiftdi_adj_3) (low[0], high[0], operands[2])); } } diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 25daeff..95220d3 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -4177,12 +4177,12 @@ && true_regnum (operands[1]) == AX_REG && true_regnum (operands[2]) == DX_REG) { - emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31))); + emit_insn (gen_ashrsi3_cvt (operands[2], operands[1], GEN_INT (31))); } else { emit_move_insn (operands[2], operands[1]); - emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31))); + emit_insn (gen_ashrsi3_cvt (operands[2], operands[2], GEN_INT (31))); } emit_move_insn (operands[4], operands[2]); DONE; @@ -4207,14 +4207,14 @@ if ((optimize_function_for_size_p (cfun) || TARGET_USE_CLTD) && true_regnum (operands[3]) == AX_REG) { - emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31))); + emit_insn (gen_ashrsi3_cvt (operands[4], operands[3], GEN_INT (31))); DONE; } if (true_regnum (operands[4]) != true_regnum (operands[1])) emit_move_insn (operands[4], operands[1]); - emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31))); + emit_insn (gen_ashrsi3_cvt (operands[4], operands[4], GEN_INT (31))); DONE; }) @@ -10209,42 +10209,40 @@ ;; See comment above `ashldi3' about how this works. -(define_expand "ashrti3" - [(set (match_operand:TI 0 "register_operand" "") - (ashiftrt:TI (match_operand:TI 1 "register_operand" "") - (match_operand:QI 2 "nonmemory_operand" "")))] - "TARGET_64BIT" - "ix86_expand_binary_operator (ASHIFTRT, TImode, operands); DONE;") +(define_expand "ashr<mode>3" + [(set (match_operand:SDWIM 0 "<shift_operand>" "") + (ashiftrt:SDWIM (match_operand:SDWIM 1 "<shift_operand>" "") + (match_operand:QI 2 "nonmemory_operand" "")))] + "" + "ix86_expand_binary_operator (ASHIFTRT, <MODE>mode, operands); DONE;") -(define_insn "*ashrti3_1" - [(set (match_operand:TI 0 "register_operand" "=r") - (ashiftrt:TI (match_operand:TI 1 "register_operand" "0") - (match_operand:QI 2 "nonmemory_operand" "Oc"))) +(define_insn_and_split "*ashr<mode>3_doubleword" + [(set (match_operand:DWI 0 "register_operand" "=r") + (ashiftrt:DWI (match_operand:DWI 1 "register_operand" "0") + (match_operand:QI 2 "nonmemory_operand" "<S>c"))) (clobber (reg:CC FLAGS_REG))] - "TARGET_64BIT" + "" "#" + "(optimize && flag_peephole2) ? epilogue_completed : reload_completed" + [(const_int 0)] + "ix86_split_ashr (operands, NULL_RTX, <MODE>mode); DONE;" [(set_attr "type" "multi")]) +;; By default we don't ask for a scratch register, because when DWImode +;; values are manipulated, registers are already at a premium. But if +;; we have one handy, we won't turn it away. + (define_peephole2 - [(match_scratch:DI 3 "r") - (parallel [(set (match_operand:TI 0 "register_operand" "") - (ashiftrt:TI (match_operand:TI 1 "register_operand" "") - (match_operand:QI 2 "nonmemory_operand" ""))) + [(match_scratch:DWIH 3 "r") + (parallel [(set (match_operand:<DWI> 0 "register_operand" "") + (ashiftrt:<DWI> + (match_operand:<DWI> 1 "register_operand" "") + (match_operand:QI 2 "nonmemory_operand" ""))) (clobber (reg:CC FLAGS_REG))]) (match_dup 3)] - "TARGET_64BIT" - [(const_int 0)] - "ix86_split_ashr (operands, operands[3], TImode); DONE;") - -(define_split - [(set (match_operand:TI 0 "register_operand" "") - (ashiftrt:TI (match_operand:TI 1 "register_operand" "") - (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC FLAGS_REG))] - "TARGET_64BIT && ((optimize > 0 && flag_peephole2) - ? epilogue_completed : reload_completed)" + "TARGET_CMOVE" [(const_int 0)] - "ix86_split_ashr (operands, NULL_RTX, TImode); DONE;") + "ix86_split_ashr (operands, operands[3], <DWI>mode); DONE;") (define_insn "x86_64_shrd" [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m") @@ -10261,45 +10259,24 @@ (set_attr "athlon_decode" "vector") (set_attr "amdfam10_decode" "vector")]) -(define_expand "ashrdi3" - [(set (match_operand:DI 0 "shiftdi_operand" "") - (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "") - (match_operand:QI 2 "nonmemory_operand" "")))] - "" - "ix86_expand_binary_operator (ASHIFTRT, DImode, operands); DONE;") - -(define_expand "x86_64_shift_adj_3" - [(use (match_operand:DI 0 "register_operand" "")) - (use (match_operand:DI 1 "register_operand" "")) - (use (match_operand:QI 2 "register_operand" ""))] +(define_insn "x86_shrd" + [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m") + (ior:SI (ashiftrt:SI (match_dup 0) + (match_operand:QI 2 "nonmemory_operand" "Ic")) + (ashift:SI (match_operand:SI 1 "register_operand" "r") + (minus:QI (const_int 32) (match_dup 2))))) + (clobber (reg:CC FLAGS_REG))] "" -{ - rtx label = gen_label_rtx (); - rtx tmp; - - emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (64))); - - tmp = gen_rtx_REG (CCZmode, FLAGS_REG); - tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx); - tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, - gen_rtx_LABEL_REF (VOIDmode, label), - pc_rtx); - tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp)); - JUMP_LABEL (tmp) = label; - - emit_move_insn (operands[0], operands[1]); - emit_insn (gen_ashrdi3_63_rex64 (operands[1], operands[1], GEN_INT (63))); - - emit_label (label); - LABEL_NUSES (label) = 1; - - DONE; -}) + "shrd{l}\t{%s2%1, %0|%0, %1, %2}" + [(set_attr "type" "ishift") + (set_attr "prefix_0f" "1") + (set_attr "pent_pair" "np") + (set_attr "mode" "SI")]) -(define_insn "ashrdi3_63_rex64" +(define_insn "ashrdi3_cvt" [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm") (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0") - (match_operand:DI 2 "const_int_operand" "i,i"))) + (match_operand:QI 2 "const_int_operand" ""))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun)) @@ -10313,158 +10290,52 @@ (set_attr "modrm" "0,1") (set_attr "mode" "DI")]) -(define_insn "*ashrdi3_1_one_bit_rex64" - [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") - (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const1_operand" ""))) - (clobber (reg:CC FLAGS_REG))] - "TARGET_64BIT - && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)) - && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)" - "sar{q}\t%0" - [(set_attr "type" "ishift") - (set_attr "length_immediate" "0") - (set_attr "mode" "DI")]) - -(define_insn "*ashrdi3_1_rex64" - [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm") - (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") - (match_operand:QI 2 "nonmemory_operand" "J,c"))) +(define_insn "*ashrsi3_cvt_zext" + [(set (match_operand:DI 0 "register_operand" "=*d,r") + (zero_extend:DI + (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0") + (match_operand:QI 2 "const_int_operand" "")))) (clobber (reg:CC FLAGS_REG))] - "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)" + "TARGET_64BIT && INTVAL (operands[2]) == 31 + && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun)) + && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" "@ - sar{q}\t{%2, %0|%0, %2} - sar{q}\t{%b2, %0|%0, %b2}" - [(set_attr "type" "ishift") - (set_attr "mode" "DI")]) - -;; This pattern can't accept a variable shift count, since shifts by -;; zero don't affect the flags. We assume that shifts by constant -;; zero are optimized away. -(define_insn "*ashrdi3_one_bit_cmp_rex64" - [(set (reg FLAGS_REG) - (compare - (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const1_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "nonimmediate_operand" "=rm") - (ashiftrt:DI (match_dup 1) (match_dup 2)))] - "TARGET_64BIT - && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)) - && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)" - "sar{q}\t%0" - [(set_attr "type" "ishift") - (set_attr "length_immediate" "0") - (set_attr "mode" "DI")]) - -(define_insn "*ashrdi3_one_bit_cconly_rex64" - [(set (reg FLAGS_REG) - (compare - (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const1_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 0 "=r"))] - "TARGET_64BIT - && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)) - && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)" - "sar{q}\t%0" - [(set_attr "type" "ishift") - (set_attr "length_immediate" "0") - (set_attr "mode" "DI")]) - -;; This pattern can't accept a variable shift count, since shifts by -;; zero don't affect the flags. We assume that shifts by constant -;; zero are optimized away. -(define_insn "*ashrdi3_cmp_rex64" - [(set (reg FLAGS_REG) - (compare - (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const_1_to_63_operand" "J")) - (const_int 0))) - (set (match_operand:DI 0 "nonimmediate_operand" "=rm") - (ashiftrt:DI (match_dup 1) (match_dup 2)))] - "TARGET_64BIT - && (optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL) - && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)" - "sar{q}\t{%2, %0|%0, %2}" - [(set_attr "type" "ishift") - (set_attr "mode" "DI")]) - -(define_insn "*ashrdi3_cconly_rex64" - [(set (reg FLAGS_REG) - (compare - (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const_1_to_63_operand" "J")) - (const_int 0))) - (clobber (match_scratch:DI 0 "=r"))] - "TARGET_64BIT - && (optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL) - && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)" - "sar{q}\t{%2, %0|%0, %2}" - [(set_attr "type" "ishift") - (set_attr "mode" "DI")]) - -(define_insn "*ashrdi3_1" - [(set (match_operand:DI 0 "register_operand" "=r") - (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") - (match_operand:QI 2 "nonmemory_operand" "Jc"))) - (clobber (reg:CC FLAGS_REG))] - "!TARGET_64BIT" - "#" - [(set_attr "type" "multi")]) - -;; By default we don't ask for a scratch register, because when DImode -;; values are manipulated, registers are already at a premium. But if -;; we have one handy, we won't turn it away. -(define_peephole2 - [(match_scratch:SI 3 "r") - (parallel [(set (match_operand:DI 0 "register_operand" "") - (ashiftrt:DI (match_operand:DI 1 "register_operand" "") - (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC FLAGS_REG))]) - (match_dup 3)] - "!TARGET_64BIT && TARGET_CMOVE" - [(const_int 0)] - "ix86_split_ashr (operands, operands[3], DImode); DONE;") - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (ashiftrt:DI (match_operand:DI 1 "register_operand" "") - (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC FLAGS_REG))] - "!TARGET_64BIT && ((optimize > 0 && flag_peephole2) - ? epilogue_completed : reload_completed)" - [(const_int 0)] - "ix86_split_ashr (operands, NULL_RTX, DImode); DONE;") + {cltd|cdq} + sar{l}\t{%2, %k0|%k0, %2}" + [(set_attr "type" "imovx,ishift") + (set_attr "prefix_0f" "0,*") + (set_attr "length_immediate" "0,*") + (set_attr "modrm" "0,1") + (set_attr "mode" "SI")]) -(define_insn "x86_shrd" - [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m") - (ior:SI (ashiftrt:SI (match_dup 0) - (match_operand:QI 2 "nonmemory_operand" "Ic")) - (ashift:SI (match_operand:SI 1 "register_operand" "r") - (minus:QI (const_int 32) (match_dup 2))))) +(define_insn "ashrsi3_cvt" + [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm") + (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0") + (match_operand:QI 2 "const_int_operand" ""))) (clobber (reg:CC FLAGS_REG))] - "" - "shrd{l}\t{%s2%1, %0|%0, %1, %2}" - [(set_attr "type" "ishift") - (set_attr "prefix_0f" "1") - (set_attr "pent_pair" "np") + "INTVAL (operands[2]) == 31 + && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun)) + && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" + "@ + {cltd|cdq} + sar{l}\t{%2, %0|%0, %2}" + [(set_attr "type" "imovx,ishift") + (set_attr "prefix_0f" "0,*") + (set_attr "length_immediate" "0,*") + (set_attr "modrm" "0,1") (set_attr "mode" "SI")]) -(define_expand "x86_shift_adj_3" - [(use (match_operand:SI 0 "register_operand" "")) - (use (match_operand:SI 1 "register_operand" "")) +(define_expand "x86_shift<mode>_adj_3" + [(use (match_operand:SWI48 0 "register_operand" "")) + (use (match_operand:SWI48 1 "register_operand" "")) (use (match_operand:QI 2 "register_operand" ""))] "" { rtx label = gen_label_rtx (); rtx tmp; - emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32))); + emit_insn (gen_testqi_ccz_1 (operands[2], + GEN_INT (GET_MODE_BITSIZE (<MODE>mode)))); tmp = gen_rtx_REG (CCZmode, FLAGS_REG); tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx); @@ -10475,193 +10346,126 @@ JUMP_LABEL (tmp) = label; emit_move_insn (operands[0], operands[1]); - emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31))); - + emit_insn (gen_ashr<mode>3_cvt (operands[1], operands[1], + GEN_INT (GET_MODE_BITSIZE (<MODE>mode)-1))); emit_label (label); LABEL_NUSES (label) = 1; DONE; }) -(define_expand "ashrsi3_31" - [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm") - (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0") - (match_operand:SI 2 "const_int_operand" "i,i"))) - (clobber (reg:CC FLAGS_REG))])] - "") - -(define_insn "*ashrsi3_31" - [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm") - (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0") - (match_operand:SI 2 "const_int_operand" "i,i"))) - (clobber (reg:CC FLAGS_REG))] - "INTVAL (operands[2]) == 31 - && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun)) - && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" - "@ - {cltd|cdq} - sar{l}\t{%2, %0|%0, %2}" - [(set_attr "type" "imovx,ishift") - (set_attr "prefix_0f" "0,*") - (set_attr "length_immediate" "0,*") - (set_attr "modrm" "0,1") - (set_attr "mode" "SI")]) - -(define_insn "*ashrsi3_31_zext" - [(set (match_operand:DI 0 "register_operand" "=*d,r") - (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0") - (match_operand:SI 2 "const_int_operand" "i,i")))) - (clobber (reg:CC FLAGS_REG))] - "TARGET_64BIT && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun)) - && INTVAL (operands[2]) == 31 - && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" - "@ - {cltd|cdq} - sar{l}\t{%2, %k0|%k0, %2}" - [(set_attr "type" "imovx,ishift") - (set_attr "prefix_0f" "0,*") - (set_attr "length_immediate" "0,*") - (set_attr "modrm" "0,1") - (set_attr "mode" "SI")]) - -(define_expand "ashrsi3" - [(set (match_operand:SI 0 "nonimmediate_operand" "") - (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "") - (match_operand:QI 2 "nonmemory_operand" "")))] - "" - "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;") - -(define_insn "*ashrsi3_1_one_bit" - [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") - (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const1_operand" ""))) - (clobber (reg:CC FLAGS_REG))] - "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun)) - && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" - "sar{l}\t%0" - [(set_attr "type" "ishift") - (set_attr "length_immediate" "0") - (set_attr "mode" "SI")]) - -(define_insn "*ashrsi3_1_one_bit_zext" - [(set (match_operand:DI 0 "register_operand" "=r") - (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:QI 2 "const1_operand" "")))) - (clobber (reg:CC FLAGS_REG))] - "TARGET_64BIT - && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)) - && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" - "sar{l}\t%k0" - [(set_attr "type" "ishift") - (set_attr "length_immediate" "0") - (set_attr "mode" "SI")]) - -(define_insn "*ashrsi3_1" - [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") - (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") - (match_operand:QI 2 "nonmemory_operand" "I,c"))) +(define_insn "*ashr<mode>3_1" + [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m") + (ashiftrt:SWI (match_operand:SWI 1 "nonimmediate_operand" "0") + (match_operand:QI 2 "nonmemory_operand" "c<S>"))) (clobber (reg:CC FLAGS_REG))] - "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" - "@ - sar{l}\t{%2, %0|%0, %2} - sar{l}\t{%b2, %0|%0, %b2}" + "ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands)" +{ + if (REG_P (operands[2])) + return "sar{<imodesuffix>}\t{%b2, %0|%0, %b2}"; + else if (operands[2] == const1_rtx + && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) + return "sar{<imodesuffix>}\t%0"; + else + return "sar{<imodesuffix>}\t{%2, %0|%0, %2}"; +} [(set_attr "type" "ishift") - (set_attr "mode" "SI")]) + (set (attr "length_immediate") + (if_then_else + (and (match_operand 2 "const1_operand" "") + (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)") + (const_int 0))) + (const_string "0") + (const_string "*"))) + (set_attr "mode" "<MODE>")]) (define_insn "*ashrsi3_1_zext" - [(set (match_operand:DI 0 "register_operand" "=r,r") - (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0") - (match_operand:QI 2 "nonmemory_operand" "I,c")))) + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:QI 2 "nonmemory_operand" "cI")))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" - "@ - sar{l}\t{%2, %k0|%k0, %2} - sar{l}\t{%b2, %k0|%k0, %b2}" - [(set_attr "type" "ishift") - (set_attr "mode" "SI")]) - -;; This pattern can't accept a variable shift count, since shifts by -;; zero don't affect the flags. We assume that shifts by constant -;; zero are optimized away. -(define_insn "*ashrsi3_one_bit_cmp" - [(set (reg FLAGS_REG) - (compare - (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const1_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "nonimmediate_operand" "=rm") - (ashiftrt:SI (match_dup 1) (match_dup 2)))] - "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun)) - && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" - "sar{l}\t%0" - [(set_attr "type" "ishift") - (set_attr "length_immediate" "0") - (set_attr "mode" "SI")]) - -(define_insn "*ashrsi3_one_bit_cconly" - [(set (reg FLAGS_REG) - (compare - (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const1_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 0 "=r"))] - "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun)) - && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" - "sar{l}\t%0" +{ + if (REG_P (operands[2])) + return "sar{l}\t{%b2, %k0|%k0, %b2}"; + else if (operands[2] == const1_rtx + && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) + return "sar{l}\t%k0"; + else + return "sar{l}\t{%2, %k0|%k0, %2}"; +} [(set_attr "type" "ishift") - (set_attr "length_immediate" "0") + (set (attr "length_immediate") + (if_then_else + (and (match_operand 2 "const1_operand" "") + (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)") + (const_int 0))) + (const_string "0") + (const_string "*"))) (set_attr "mode" "SI")]) -(define_insn "*ashrsi3_one_bit_cmp_zext" - [(set (reg FLAGS_REG) - (compare - (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:QI 2 "const1_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "register_operand" "=r") - (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))] - "TARGET_64BIT - && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)) - && ix86_match_ccmode (insn, CCmode) - && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" - "sar{l}\t%k0" - [(set_attr "type" "ishift") - (set_attr "length_immediate" "0") - (set_attr "mode" "SI")]) +(define_insn "*ashrqi3_1_slp" + [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) + (ashiftrt:QI (match_dup 0) + (match_operand:QI 1 "nonmemory_operand" "cI"))) + (clobber (reg:CC FLAGS_REG))] + "(optimize_function_for_size_p (cfun) + || !TARGET_PARTIAL_REG_STALL + || (operands[1] == const1_rtx + && TARGET_SHIFT1))" +{ + if (REG_P (operands[1])) + return "sar{b}\t{%b1, %0|%0, %b1}"; + else if (operands[1] == const1_rtx + && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) + return "sar{b}\t%0"; + else + return "sar{b}\t{%1, %0|%0, %1}"; +} + [(set_attr "type" "ishift1") + (set (attr "length_immediate") + (if_then_else + (and (match_operand 1 "const1_operand" "") + (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)") + (const_int 0))) + (const_string "0") + (const_string "*"))) + (set_attr "mode" "QI")]) ;; This pattern can't accept a variable shift count, since shifts by ;; zero don't affect the flags. We assume that shifts by constant ;; zero are optimized away. -(define_insn "*ashrsi3_cmp" +(define_insn "*ashr<mode>3_cmp" [(set (reg FLAGS_REG) (compare - (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const_1_to_31_operand" "I")) + (ashiftrt:SWI (match_operand:SWI 1 "nonimmediate_operand" "0") + (match_operand:QI 2 "<shift_immediate_operand>" "<S>")) (const_int 0))) - (set (match_operand:SI 0 "nonimmediate_operand" "=rm") - (ashiftrt:SI (match_dup 1) (match_dup 2)))] - "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL) - && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" - "sar{l}\t{%2, %0|%0, %2}" - [(set_attr "type" "ishift") - (set_attr "mode" "SI")]) - -(define_insn "*ashrsi3_cconly" - [(set (reg FLAGS_REG) - (compare - (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const_1_to_31_operand" "I")) - (const_int 0))) - (clobber (match_scratch:SI 0 "=r"))] - "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL) + (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m") + (ashiftrt:SWI (match_dup 1) (match_dup 2)))] + "(optimize_function_for_size_p (cfun) + || !TARGET_PARTIAL_FLAG_REG_STALL + || (operands[2] == const1_rtx + && TARGET_SHIFT1)) && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" - "sar{l}\t{%2, %0|%0, %2}" + && ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands)" +{ + if (operands[2] == const1_rtx + && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) + return "sar{<imodesuffix>}\t%0"; + else + return "sar{<imodesuffix>}\t{%2, %0|%0, %2}"; +} [(set_attr "type" "ishift") - (set_attr "mode" "SI")]) + (set (attr "length_immediate") + (if_then_else + (and (match_operand 2 "const1_operand" "") + (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)") + (const_int 0))) + (const_string "0") + (const_string "*"))) + (set_attr "mode" "<MODE>")]) (define_insn "*ashrsi3_cmp_zext" [(set (reg FLAGS_REG) @@ -10672,233 +10476,58 @@ (set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))] "TARGET_64BIT - && (optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL) + && (optimize_function_for_size_p (cfun) + || !TARGET_PARTIAL_FLAG_REG_STALL + || (operands[2] == const1_rtx + && TARGET_SHIFT1)) && ix86_match_ccmode (insn, CCGOCmode) && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" - "sar{l}\t{%2, %k0|%k0, %2}" +{ + if (operands[2] == const1_rtx + && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) + return "sar{l}\t%k0"; + else + return "sar{l}\t{%2, %k0|%k0, %2}"; +} [(set_attr "type" "ishift") + (set (attr "length_immediate") + (if_then_else + (and (match_operand 2 "const1_operand" "") + (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)") + (const_int 0))) + (const_string "0") + (const_string "*"))) (set_attr "mode" "SI")]) -(define_expand "ashrhi3" - [(set (match_operand:HI 0 "nonimmediate_operand" "") - (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "") - (match_operand:QI 2 "nonmemory_operand" "")))] - "TARGET_HIMODE_MATH" - "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;") - -(define_insn "*ashrhi3_1_one_bit" - [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") - (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const1_operand" ""))) - (clobber (reg:CC FLAGS_REG))] - "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun)) - && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)" - "sar{w}\t%0" - [(set_attr "type" "ishift") - (set_attr "length_immediate" "0") - (set_attr "mode" "HI")]) - -(define_insn "*ashrhi3_1" - [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm") - (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") - (match_operand:QI 2 "nonmemory_operand" "I,c"))) - (clobber (reg:CC FLAGS_REG))] - "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)" - "@ - sar{w}\t{%2, %0|%0, %2} - sar{w}\t{%b2, %0|%0, %b2}" - [(set_attr "type" "ishift") - (set_attr "mode" "HI")]) - -;; This pattern can't accept a variable shift count, since shifts by -;; zero don't affect the flags. We assume that shifts by constant -;; zero are optimized away. -(define_insn "*ashrhi3_one_bit_cmp" - [(set (reg FLAGS_REG) - (compare - (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const1_operand" "")) - (const_int 0))) - (set (match_operand:HI 0 "nonimmediate_operand" "=rm") - (ashiftrt:HI (match_dup 1) (match_dup 2)))] - "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun)) - && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)" - "sar{w}\t%0" - [(set_attr "type" "ishift") - (set_attr "length_immediate" "0") - (set_attr "mode" "HI")]) - -(define_insn "*ashrhi3_one_bit_cconly" - [(set (reg FLAGS_REG) - (compare - (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const1_operand" "")) - (const_int 0))) - (clobber (match_scratch:HI 0 "=r"))] - "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun)) - && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)" - "sar{w}\t%0" - [(set_attr "type" "ishift") - (set_attr "length_immediate" "0") - (set_attr "mode" "HI")]) - -;; This pattern can't accept a variable shift count, since shifts by -;; zero don't affect the flags. We assume that shifts by constant -;; zero are optimized away. -(define_insn "*ashrhi3_cmp" - [(set (reg FLAGS_REG) - (compare - (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const_1_to_31_operand" "I")) - (const_int 0))) - (set (match_operand:HI 0 "nonimmediate_operand" "=rm") - (ashiftrt:HI (match_dup 1) (match_dup 2)))] - "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL) - && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)" - "sar{w}\t{%2, %0|%0, %2}" - [(set_attr "type" "ishift") - (set_attr "mode" "HI")]) - -(define_insn "*ashrhi3_cconly" - [(set (reg FLAGS_REG) - (compare - (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const_1_to_31_operand" "I")) - (const_int 0))) - (clobber (match_scratch:HI 0 "=r"))] - "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL) - && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)" - "sar{w}\t{%2, %0|%0, %2}" - [(set_attr "type" "ishift") - (set_attr "mode" "HI")]) - -(define_expand "ashrqi3" - [(set (match_operand:QI 0 "nonimmediate_operand" "") - (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "") - (match_operand:QI 2 "nonmemory_operand" "")))] - "TARGET_QIMODE_MATH" - "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;") - -(define_insn "*ashrqi3_1_one_bit" - [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") - (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const1_operand" ""))) - (clobber (reg:CC FLAGS_REG))] - "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun)) - && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" - "sar{b}\t%0" - [(set_attr "type" "ishift") - (set_attr "length_immediate" "0") - (set_attr "mode" "QI")]) - -(define_insn "*ashrqi3_1_one_bit_slp" - [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) - (ashiftrt:QI (match_dup 0) - (match_operand:QI 1 "const1_operand" ""))) - (clobber (reg:CC FLAGS_REG))] - "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) - && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)) - && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" - "sar{b}\t%0" - [(set_attr "type" "ishift1") - (set_attr "length_immediate" "0") - (set_attr "mode" "QI")]) - -(define_insn "*ashrqi3_1" - [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm") - (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") - (match_operand:QI 2 "nonmemory_operand" "I,c"))) - (clobber (reg:CC FLAGS_REG))] - "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" - "@ - sar{b}\t{%2, %0|%0, %2} - sar{b}\t{%b2, %0|%0, %b2}" - [(set_attr "type" "ishift") - (set_attr "mode" "QI")]) - -(define_insn "*ashrqi3_1_slp" - [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm")) - (ashiftrt:QI (match_dup 0) - (match_operand:QI 1 "nonmemory_operand" "I,c"))) - (clobber (reg:CC FLAGS_REG))] - "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) - && !(MEM_P (operands[0]) && MEM_P (operands[1]))" - "@ - sar{b}\t{%1, %0|%0, %1} - sar{b}\t{%b1, %0|%0, %b1}" - [(set_attr "type" "ishift1") - (set_attr "mode" "QI")]) - -;; This pattern can't accept a variable shift count, since shifts by -;; zero don't affect the flags. We assume that shifts by constant -;; zero are optimized away. -(define_insn "*ashrqi3_one_bit_cmp" - [(set (reg FLAGS_REG) - (compare - (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const1_operand" "I")) - (const_int 0))) - (set (match_operand:QI 0 "nonimmediate_operand" "=qm") - (ashiftrt:QI (match_dup 1) (match_dup 2)))] - "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun)) - && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" - "sar{b}\t%0" - [(set_attr "type" "ishift") - (set_attr "length_immediate" "0") - (set_attr "mode" "QI")]) - -(define_insn "*ashrqi3_one_bit_cconly" +(define_insn "*ashr<mode>3_cconly" [(set (reg FLAGS_REG) (compare - (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const1_operand" "")) + (ashiftrt:SWI (match_operand:SWI 1 "nonimmediate_operand" "0") + (match_operand:QI 2 "<shift_immediate_operand>" "<S>")) (const_int 0))) - (clobber (match_scratch:QI 0 "=q"))] - "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun)) - && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" - "sar{b}\t%0" - [(set_attr "type" "ishift") - (set_attr "length_immediate" "0") - (set_attr "mode" "QI")]) - -;; This pattern can't accept a variable shift count, since shifts by -;; zero don't affect the flags. We assume that shifts by constant -;; zero are optimized away. -(define_insn "*ashrqi3_cmp" - [(set (reg FLAGS_REG) - (compare - (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const_1_to_31_operand" "I")) - (const_int 0))) - (set (match_operand:QI 0 "nonimmediate_operand" "=qm") - (ashiftrt:QI (match_dup 1) (match_dup 2)))] - "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL) - && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" - "sar{b}\t{%2, %0|%0, %2}" - [(set_attr "type" "ishift") - (set_attr "mode" "QI")]) - -(define_insn "*ashrqi3_cconly" - [(set (reg FLAGS_REG) - (compare - (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const_1_to_31_operand" "I")) - (const_int 0))) - (clobber (match_scratch:QI 0 "=q"))] - "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL) + (clobber (match_scratch:DI 0 "=<r>"))] + "(optimize_function_for_size_p (cfun) + || !TARGET_PARTIAL_FLAG_REG_STALL + || (operands[2] == const1_rtx + && TARGET_SHIFT1)) && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" - "sar{b}\t{%2, %0|%0, %2}" + && ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands)" +{ + if (operands[2] == const1_rtx + && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) + return "sar{<imodesuffix>}\t%0"; + else + return "sar{<imodesuffix>}\t{%2, %0|%0, %2}"; +} [(set_attr "type" "ishift") - (set_attr "mode" "QI")]) - + (set (attr "length_immediate") + (if_then_else + (and (match_operand 2 "const1_operand" "") + (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)") + (const_int 0))) + (const_string "0") + (const_string "*"))) + (set_attr "mode" "<MODE>")]) ;; Logical shift instructions diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c7b9ccf..a7ef676 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -54,15 +54,15 @@ * g++.dg/other/pr35504.C: Add check for thiscall. * g++.dg/torture/stackalign/eh-thiscall-1.C: New. * gcc.dg/torture/stackalign/thiscall-1.c: New. - + 2010-04-09 Manuel López-Ibáñez <manu@gcc.gnu.org> PR c++/28584 * gcc.dg/Wint-to-pointer-cast-1.c: Move to... * c-c++-common/Wint-to-pointer-cast-1.c: ... here. - * gcc.dg/Wint-to-pointer-cast-2.c: Move to... + * gcc.dg/Wint-to-pointer-cast-2.c: Move to... * c-c++-common/Wint-to-pointer-cast-2.c: ... here. - * gcc.dg/Wint-to-pointer-cast-3.c: Move to... + * gcc.dg/Wint-to-pointer-cast-3.c: Move to... * c-c++-common/Wint-to-pointer-cast-3.c: ... here. Update. * g++.old-deja/g++.mike/warn1.C: Add -Wno-int-to-pointer-cast. * g++.dg/other/increment1.C: Likewise. @@ -218,7 +218,7 @@ 2010-04-06 Dodji Seketeli <dodji@redhat.com> - * g++.dg/debug/dwarf2/redeclaration-1.C: Moved from + * g++.dg/debug/dwarf2/redeclaration-1.C: Moved from c-c++-common/dwarf2/redeclaration-1.C 2010-04-06 Jason Merrill <jason@redhat.com> @@ -388,7 +388,7 @@ PR tree-optimization/43141 * gcc.dg/guality/pr43141.c: New test. - + 2010-04-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> * g++.dg/cpp/_Pragma1.C: Skip on alpha*-dec-osf*. @@ -701,13 +701,13 @@ * objc/execute/class_self-2.m: Include <stdlib.h>. * objc/execute/forward-1.x: Do not XFAIL for 32bit powerpc-darwin. * objc.dg/desig-init-1.m: Use shared wrapper headers (Object1.h, - Protocol1.h) and next-mapping.h as required. XFAIL run if NeXT + Protocol1.h) and next-mapping.h as required. XFAIL run if NeXT and 64bit. Use new NeXT interface as required. * objc.dg/special/unclaimed-category-1.m: Ditto. * objc.dg/special/unclaimed-category-1.h: Ditto. * objc.dg/special/unclaimed-category-1a.m: Ditto. * objc.dg/func-ptr-1.m: Ditto. - * objc.dg/stret-1.m: Ditto. + * objc.dg/stret-1.m: Ditto. * objc.dg/encode-2.m: Ditto. * objc.dg/category-1.m: Ditto. * objc.dg/encode-3.m: Ditto. @@ -727,10 +727,10 @@ * objc.dg/call-super-1.m: Ditto. * objc.dg/type-size-2.m: Ditto. * objc.dg/method-10.m: Ditto. - * objc.dg/defs.m: Ditto. + * objc.dg/defs.m: Ditto. * objc.dg/const-str-3.m: Ditto. * objc.dg/try-catch-6.m: Use shared wrapper headers (Object1.h, - Protocol1.h) and next-mapping.h as required. Use new NeXT + Protocol1.h) and next-mapping.h as required. Use new NeXT interface as required. * objc.dg/super-class-4.m: Ditto. * objc.dg/comp-types-8.m: Ditto. @@ -791,8 +791,7 @@ * objc.dg/try-catch-5.m: Ditto. * objc.dg/const-str-10.m: Use shared wrapper headers (Object1.h, Protocol1.h) and next-mapping.h as required. Use new NeXT - interface as required. Skip for gnu-runtime. Test for .quad - at m64. + interface as required. Skip for gnu-runtime. Test for .quad at m64. * objc.dg/const-str-11.m: Ditto. * objc.dg/const-str-9.m: Ditto. * objc.dg/method-4.m: Skip for 64Bit NeXT. |