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| author | Pan Li <pan2.li@intel.com> | 2023-11-29 14:31:30 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-11-29 14:50:29 +0800 |
| commit | 25a51e98fdd504826a40775a5e5b9ffb336b5aa1 (patch) | |
| tree | ae499715ac0816cc62fd9b681a33f7f4eb2c22ee /gcc | |
| parent | 4ed0740c6e807460ce79a351094329fdeb551545 (diff) | |
| download | gcc-25a51e98fdd504826a40775a5e5b9ffb336b5aa1.zip gcc-25a51e98fdd504826a40775a5e5b9ffb336b5aa1.tar.gz gcc-25a51e98fdd504826a40775a5e5b9ffb336b5aa1.tar.bz2 | |
RISC-V: Bugfix for ICE in block move when zve32f
The exact_div requires the exactly multiple of the divider.
Unfortunately, the condition will be broken when zve32f in
some cases. For example,
potential_ew is 8
BYTES_PER_RISCV_VECTOR * lmul1 is [4, 4]
This patch would like to ensure the precondition of exact_div
when get_vec_mode.
PR target/112743
gcc/ChangeLog:
* config/riscv/riscv-string.cc (expand_block_move): Add
precondition check for exact_div.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr112743-1.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv-string.cc | 1 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-1.c | 16 |
2 files changed, 17 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc index 3b5e05e..80e3b59 100644 --- a/gcc/config/riscv/riscv-string.cc +++ b/gcc/config/riscv/riscv-string.cc @@ -866,6 +866,7 @@ expand_block_move (rtx dst_in, rtx src_in, rtx length_in) if (TARGET_MIN_VLEN * lmul <= nunits * BITS_PER_UNIT /* Avoid loosing the option of using vsetivli . */ && (nunits <= 31 * lmul || nunits > 31 * 8) + && multiple_p (BYTES_PER_RISCV_VECTOR * lmul, potential_ew) && (riscv_vector::get_vector_mode (elem_mode, exact_div (BYTES_PER_RISCV_VECTOR * lmul, potential_ew)).exists (&vmode))) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-1.c new file mode 100644 index 0000000..2e62e60 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-1.c @@ -0,0 +1,16 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvfh_zfh -mabi=lp64 -O2" } */ + +typedef struct test_a { + void *x; + char a[10]; + short b[2]; + int c[1]; +} test_type_t; + +void +test_copy_memory (test_type_t *out, test_type_t *in) +{ + *out = *in; +} |