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| author | Jin Ma <jinma@linux.alibaba.com> | 2025-02-14 14:58:49 +0800 |
|---|---|---|
| committer | Jin Ma <jinma@linux.alibaba.com> | 2025-02-15 16:04:34 +0800 |
| commit | 25a103feb3056bc483a1558af315be452060035b (patch) | |
| tree | e552f46d5c1f06570b6066f576aacdfd4b690ebf /gcc | |
| parent | 112ac3a3ab244322f74fecd5547fcc4883e5e15a (diff) | |
| download | gcc-25a103feb3056bc483a1558af315be452060035b.zip gcc-25a103feb3056bc483a1558af315be452060035b.tar.gz gcc-25a103feb3056bc483a1558af315be452060035b.tar.bz2 | |
RISC-V: Bugfix ICE for RVV intrinisc when using no-extension parameters
When using riscv_v_abi, the return and arguments of the function should
be adequately checked to avoid ICE.
PR target/118872
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_fntype_abi): Strengthen the logic
of the check to avoid missing the error report.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr118872.c: New test.
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Jin Ma <jinma@linux.alibaba.com>
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv.cc | 10 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c | 13 |
2 files changed, 20 insertions, 3 deletions
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 6e14126..9bf7713 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -6479,9 +6479,13 @@ riscv_fntype_abi (const_tree fntype) /* Implement the vector calling convention. For more details please reference the below link. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/389 */ - if (riscv_return_value_is_vector_type_p (fntype) - || riscv_arguments_is_vector_type_p (fntype) - || riscv_vector_cc_function_p (fntype)) + bool validate_v_abi_p = false; + + validate_v_abi_p |= riscv_return_value_is_vector_type_p (fntype); + validate_v_abi_p |= riscv_arguments_is_vector_type_p (fntype); + validate_v_abi_p |= riscv_vector_cc_function_p (fntype); + + if (validate_v_abi_p) return riscv_v_abi (); return default_function_abi; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c new file mode 100644 index 0000000..adb54d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c @@ -0,0 +1,13 @@ +/* Test that we do not have ice when compile */ +/* { dg-do assemble } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" { target { rv64 } } } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O2" { target { rv32 } } } */ + +#include <riscv_vector.h> + +vfloat32m2_t foo (vfloat16m1_t a, size_t vl) +{ + return __riscv_vfwcvt_f_f_v_f32m2(a, vl); +} + +/* { dg-error "argument type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */ |