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| author | Kewen Lin <linkw@linux.ibm.com> | 2024-11-21 07:41:33 +0000 |
|---|---|---|
| committer | Kewen Lin <linkw@gcc.gnu.org> | 2024-11-21 07:41:33 +0000 |
| commit | 2441dc2495d257c4894a4d0c8d36cfbdc851579c (patch) | |
| tree | c4c636df0f38995b15d6613d46d1a29e77a1c587 /gcc | |
| parent | 0719ade048d66c91eebdcce07ae69e90a8385e1e (diff) | |
| download | gcc-2441dc2495d257c4894a4d0c8d36cfbdc851579c.zip gcc-2441dc2495d257c4894a4d0c8d36cfbdc851579c.tar.gz gcc-2441dc2495d257c4894a4d0c8d36cfbdc851579c.tar.bz2 | |
rs6000: Add veqv support to *eqv<mode>3_internal1
When making patch to replace TARGET_P8_VECTOR, I noticed
for *eqv<BOOL_128:mode>3_internal1 unlike the other logical
operations, we only exploited the vsx version. I think it
is an oversight, this patch is to consider veqv as well.
gcc/ChangeLog:
* config/rs6000/rs6000.md (*eqv<BOOL_128:mode>3_internal1): Generate
insn veqv if TARGET_ALTIVEC and operands are altivec_register_operand.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 2598059..ca91a24 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -7557,9 +7557,12 @@ (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))] "TARGET_P8_VECTOR" { - if (vsx_register_operand (operands[0], <MODE>mode)) + if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode)) return "xxleqv %x0,%x1,%x2"; + if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode)) + return "veqv %0,%1,%2"; + return "#"; } "TARGET_P8_VECTOR && reload_completed |