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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-11-07 19:46:34 +0800 |
|---|---|---|
| committer | Lehua Ding <lehua.ding@rivai.ai> | 2023-11-07 20:12:55 +0800 |
| commit | 204186bae107f9f54ed4ea0f94619431860c6b97 (patch) | |
| tree | ba8f2eae41c0dabe3d796cb753af2d5f3c2b34f9 /gcc | |
| parent | e87bc7dc08a1bd05f07781edf064db26456102d5 (diff) | |
| download | gcc-204186bae107f9f54ed4ea0f94619431860c6b97.zip gcc-204186bae107f9f54ed4ea0f94619431860c6b97.tar.gz gcc-204186bae107f9f54ed4ea0f94619431860c6b97.tar.bz2 | |
RISC-V: Add RISC-V into vect_cmdline_needed
Like all other targets, we add RISC-V into vect_cmdline_needed.
This patch fixes following FAILs:
FAIL: gcc.dg/tree-ssa/gen-vect-11b.c scan-tree-dump-times vect "vectorized 0 loops" 1
FAIL: gcc.dg/tree-ssa/gen-vect-11c.c scan-tree-dump-times vect "vectorized 0 loops" 1
FAIL: gcc.dg/tree-ssa/gen-vect-26.c scan-tree-dump-times vect "Alignment of access forced using peeling" 1
FAIL: gcc.dg/tree-ssa/gen-vect-28.c scan-tree-dump-times vect "Alignment of access forced using peeling" 1
gcc/testsuite/ChangeLog:
* lib/target-supports.exp: Add RISC-V.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/lib/target-supports.exp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 6ef53e0..0317fc1 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -4036,7 +4036,8 @@ proc check_effective_target_vect_cmdline_needed { } { || ([istarget sparc*-*-*] && [check_effective_target_sparc_vis]) || ([istarget arm*-*-*] && [check_effective_target_arm_neon]) || [istarget aarch64*-*-*] - || [istarget amdgcn*-*-*]} { + || [istarget amdgcn*-*-*] + || [istarget riscv*-*-*]} { return 0 } else { return 1 |