constraints.md: New file.

        * config/ia64/constraints.md: New file.
        * config/ia64/predicates.md: Replace CONST_OK_FOR_? with
        satisfies_constraint_?.
        * config/ia64/ia64.c (ia64_move_ok, ia64_legitimate_constant_p,
        ia64_reload_gp, spill_restore_mem, ia64_expand_prologue,
        ia64_expand_epilogue, ia64_split_return_addr_rtx, ia64_rtx_costs,
        ia64_output_mi_thunk): Likewise.
        (ia64_const_ok_for_letter_p): Remove.
        (ia64_const_double_ok_for_letter_p): Remove. 
        (ia64_extra_constraint): Remove.
        * config/ia64/ia64.h (REG_CLASS_FROM_LETTER): Remove.
        (CONST_OK_FOR_I, CONST_OK_FOR_J, CONST_OK_FOR_K, CONST_OK_FOR_L,
        CONST_OK_FOR_M, CONST_OK_FOR_N, CONST_OK_FOR_O, CONST_OK_FOR_P,
        CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_G,
        CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT,
        EXTRA_MEMORY_CONSTRAINT): Remove.
        * config/ia64/ia64.md: Include constriants.md.  Replace
        CONST_OK_FOR_? with satisfies_constraint_?.

From-SVN: r123186

7 files changed, 209 insertions, 212 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3f12200..acb54ae 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,24 @@
+2007-03-24  Richard Henderson  <rth@redhat.com>
+
+	* config/ia64/constraints.md: New file.
+	* config/ia64/predicates.md: Replace CONST_OK_FOR_? with
+	satisfies_constraint_?.
+	* config/ia64/ia64.c (ia64_move_ok, ia64_legitimate_constant_p,
+	ia64_reload_gp, spill_restore_mem, ia64_expand_prologue,
+	ia64_expand_epilogue, ia64_split_return_addr_rtx, ia64_rtx_costs,
+	ia64_output_mi_thunk): Likewise.
+	(ia64_const_ok_for_letter_p): Remove.
+	(ia64_const_double_ok_for_letter_p): Remove.
+	(ia64_extra_constraint): Remove.
+	* config/ia64/ia64.h (REG_CLASS_FROM_LETTER): Remove.
+	(CONST_OK_FOR_I, CONST_OK_FOR_J, CONST_OK_FOR_K, CONST_OK_FOR_L,
+	CONST_OK_FOR_M, CONST_OK_FOR_N, CONST_OK_FOR_O, CONST_OK_FOR_P,
+	CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_G,
+	CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT,
+	EXTRA_MEMORY_CONSTRAINT): Remove.
+	* config/ia64/ia64.md: Include constriants.md.  Replace
+	CONST_OK_FOR_? with satisfies_constraint_?.
+
 2007-03-23  Michael Meissner  <michael.meissner@amd.com>
 	    H.J. Lu  <hongjiu.lu@intel.com>
 
diff --git a/gcc/config/ia64/constraints.md b/gcc/config/ia64/constraints.md
new file mode 100644
index 0000000..a3d84d9
--- /dev/null
+++ b/gcc/config/ia64/constraints.md
@@ -0,0 +1,139 @@
+;; Constraint definitions for IA-64
+;; Copyright (C) 2006 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+;; Boston, MA 02110-1301, USA.
+
+;; Register constraints
+
+(define_register_constraint "a" "ADDL_REGS"
+  "addl register")
+
+(define_register_constraint "b" "BR_REGS"
+  "branch register")
+
+(define_register_constraint "c" "PR_REGS"
+  "predicate register")
+
+(define_register_constraint "d" "AR_M_REGS"
+  "memory pipeline application register")
+
+(define_register_constraint "e" "AR_I_REGS"
+  "integer pipeline application register")
+
+(define_register_constraint "f" "FR_REGS"
+  "floating-point register")
+
+(define_register_constraint "x" "FP_REGS"
+  "floating-point register, excluding f31 and f127, used for fldp")
+
+;; Integer constraints
+
+(define_constraint "I"
+  "14 bit signed immediate for arithmetic instructions"
+  (and (match_code "const_int")
+       (match_test "(unsigned HOST_WIDE_INT)ival + 0x2000 < 0x4000")))
+
+(define_constraint "J"
+  "22 bit signed immediate for arith instructions with r0/r1/r2/r3 source"
+  (and (match_code "const_int")
+       (match_test "(unsigned HOST_WIDE_INT)ival + 0x200000 < 0x400000")))
+
+(define_constraint "K"
+  "8 bit signed immediate for logical instructions"
+  (and (match_code "const_int")
+       (match_test "(unsigned HOST_WIDE_INT)ival + 0x80 < 0x100")))
+
+(define_constraint "L"
+  "8 bit adjusted signed immediate for compare pseudo-ops"
+  (and (match_code "const_int")
+       (match_test "(unsigned HOST_WIDE_INT)ival + 0x7F < 0x100")))
+
+(define_constraint "M"
+  "6 bit unsigned immediate for shift counts"
+  (and (match_code "const_int")
+       (match_test "(unsigned HOST_WIDE_INT)ival < 0x40")))
+
+(define_constraint "N"
+  "9 bit signed immediate for load/store post-increments"
+  (and (match_code "const_int")
+       (match_test "(unsigned HOST_WIDE_INT)ival + 0x100 < 0x200")))
+
+(define_constraint "O"
+  "constant zero"
+  (and (match_code "const_int")
+       (match_test "ival == 0")))
+
+(define_constraint "P"
+  "0 or -1 for dep instruction"
+  (and (match_code "const_int")
+       (match_test "ival == 0 || ival == -1")))
+
+;; Floating-point constraints
+
+(define_constraint "G"
+  "0.0 and 1.0 for fr0 and fr1"
+  (and (match_code "const_double")
+       (match_test "op == CONST0_RTX (mode) || op == CONST1_RTX (mode)")))
+
+;; Extra constraints
+
+;; Note that while this accepts mem, it only accepts non-volatile mem,
+;; and so cannot be "fixed" by adjusting the address.  Thus it cannot
+;; and does not use define_memory_constraint.
+(define_constraint "Q"
+  "Non-volatile memory for FP_REG loads/stores"
+  (and (match_operand 0 "memory_operand")
+       (match_test "!MEM_VOLATILE_P (op)")))
+
+(define_constraint "R"
+  "1..4 for shladd arguments"
+  (and (match_code "const_int")
+       (match_test "ival >= 1 && ival <= 4")))
+
+(define_constraint "T"
+  "Symbol ref to small-address-area"
+  (match_operand 0 "small_addr_symbolic_operand"))
+
+;; ??? Original definition didn't test for vector only.  
+;; Need to verify that only used in vector context.
+(define_constraint "U"
+  "vector zero constant"
+  (and (match_code "const_int,const_double,const_vector")
+       (match_test "op == CONST0_RTX (mode)")))
+
+(define_constraint "W"
+  "An integer vector, such that conversion to an integer yields a
+   value appropriate for an integer 'J' constraint."
+  (and (match_code "const_vector")
+       (match_test "GET_MODE_CLASS (mode) == MODE_VECTOR_INT")
+       (match_test
+	"satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
+
+(define_constraint "Y"
+  "A V2SF vector containing elements that satisfy 'G'"
+  (and (match_code "const_vector")
+       (match_test "mode == V2SFmode")
+       (match_test "satisfies_constraint_G (XVECEXP (op, 0, 0))")
+       (match_test "satisfies_constraint_G (XVECEXP (op, 0, 1))")))
+
+;; Memory constraints
+
+(define_memory_constraint "S"
+  "Non-post-inc memory for asms and other unsavory creatures"
+  (and (match_code "mem")
+       (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC")))
diff --git a/gcc/config/ia64/ia64-protos.h b/gcc/config/ia64/ia64-protos.h
index c4bf61d..555038b 100644
--- a/gcc/config/ia64/ia64-protos.h
+++ b/gcc/config/ia64/ia64-protos.h
@@ -34,9 +34,6 @@ extern int ia64_st_address_bypass_p (rtx, rtx);
 extern int ia64_ld_address_bypass_p (rtx, rtx);
 extern int ia64_produce_address_p (rtx);
 
-extern bool ia64_const_ok_for_letter_p (HOST_WIDE_INT, char);
-extern bool ia64_const_double_ok_for_letter_p (rtx, char);
-extern bool ia64_extra_constraint (rtx, char);
 extern bool ia64_legitimate_constant_p (rtx);
 
 extern rtx ia64_expand_move (rtx, rtx);
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index dc10abb..2bbd681 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -55,6 +55,7 @@ Boston, MA 02110-1301, USA.  */
 #include "intl.h"
 #include "debug.h"
 #include "params.h"
+#include "tm-constrs.h"
 
 /* This is used for communication between ASM_OUTPUT_LABEL and
    ASM_OUTPUT_LABELREF.  */
@@ -602,102 +603,6 @@ ia64_encode_section_info (tree decl, rtx rtl, int first)
     ia64_encode_addr_area (decl, XEXP (rtl, 0));
 }
 
-/* Implement CONST_OK_FOR_LETTER_P.  */
-
-bool
-ia64_const_ok_for_letter_p (HOST_WIDE_INT value, char c)
-{
-  switch (c)
-    {
-    case 'I':
-      return CONST_OK_FOR_I (value);
-    case 'J':
-      return CONST_OK_FOR_J (value);
-    case 'K':
-      return CONST_OK_FOR_K (value);
-    case 'L':
-      return CONST_OK_FOR_L (value);
-    case 'M':
-      return CONST_OK_FOR_M (value);
-    case 'N':
-      return CONST_OK_FOR_N (value);
-    case 'O':
-      return CONST_OK_FOR_O (value);
-    case 'P':
-      return CONST_OK_FOR_P (value);
-    default:
-      return false;
-    }
-}
-
-/* Implement CONST_DOUBLE_OK_FOR_LETTER_P.  */
-
-bool
-ia64_const_double_ok_for_letter_p (rtx value, char c)
-{
-  switch (c)
-    {
-    case 'G':
-      return CONST_DOUBLE_OK_FOR_G (value);
-    default:
-      return false;
-    }
-}
-
-/* Implement EXTRA_CONSTRAINT.  */
-
-bool
-ia64_extra_constraint (rtx value, char c)
-{
-  switch (c)
-    {
-    case 'Q':
-      /* Non-volatile memory for FP_REG loads/stores.  */
-      return memory_operand(value, VOIDmode) && !MEM_VOLATILE_P (value);
-
-    case 'R':
-      /* 1..4 for shladd arguments.  */
-      return (GET_CODE (value) == CONST_INT
-	      && INTVAL (value) >= 1 && INTVAL (value) <= 4);
-
-    case 'S':
-      /* Non-post-inc memory for asms and other unsavory creatures.  */
-      return (GET_CODE (value) == MEM
-	      && GET_RTX_CLASS (GET_CODE (XEXP (value, 0))) != RTX_AUTOINC
-	      && (reload_in_progress || memory_operand (value, VOIDmode)));
-
-    case 'T':
-      /* Symbol ref to small-address-area.  */
-      return small_addr_symbolic_operand (value, VOIDmode);
-
-    case 'U':
-      /* Vector zero.  */
-      return value == CONST0_RTX (GET_MODE (value));
-
-    case 'W':
-      /* An integer vector, such that conversion to an integer yields a
-	 value appropriate for an integer 'J' constraint.  */
-      if (GET_CODE (value) == CONST_VECTOR
-	  && GET_MODE_CLASS (GET_MODE (value)) == MODE_VECTOR_INT)
-	{
-	  value = simplify_subreg (DImode, value, GET_MODE (value), 0);
-	  return ia64_const_ok_for_letter_p (INTVAL (value), 'J');
-	}
-      return false;
-
-    case 'Y':
-      /* A V2SF vector containing elements that satisfy 'G'.  */
-      return
-	(GET_CODE (value) == CONST_VECTOR
-	 && GET_MODE (value) == V2SFmode
-	 && ia64_const_double_ok_for_letter_p (XVECEXP (value, 0, 0), 'G')
-	 && ia64_const_double_ok_for_letter_p (XVECEXP (value, 0, 1), 'G'));
-
-    default:
-      return false;
-    }
-}
-
 /* Return 1 if the operands of a move are ok.  */
 
 int
@@ -718,7 +623,7 @@ ia64_move_ok (rtx dst, rtx src)
   if (INTEGRAL_MODE_P (GET_MODE (dst)))
     return src == const0_rtx;
   else
-    return GET_CODE (src) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_G (src);
+    return satisfies_constraint_G (src);
 }
 
 /* Return 1 if the operands are ok for a floating point load pair.  */
@@ -809,7 +714,7 @@ ia64_legitimate_constant_p (rtx x)
     case CONST_DOUBLE:
       if (GET_MODE (x) == VOIDmode)
 	return true;
-      return CONST_DOUBLE_OK_FOR_G (x);
+      return satisfies_constraint_G (x);
 
     case CONST:
     case SYMBOL_REF:
@@ -843,7 +748,7 @@ ia64_legitimate_constant_p (rtx x)
 	enum machine_mode mode = GET_MODE (x);
 
 	if (mode == V2SFmode)
-	  return ia64_extra_constraint (x, 'Y');
+	  return satisfies_constraint_Y (x);
 
 	return (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
 		&& GET_MODE_SIZE (mode) <= 8);
@@ -1977,6 +1882,7 @@ ia64_reload_gp (void)
   else
     {
       HOST_WIDE_INT offset;
+      rtx offset_r;
 
       offset = (current_frame_info.spill_cfa_off
 	        + current_frame_info.spill_size);
@@ -1991,12 +1897,12 @@ ia64_reload_gp (void)
           offset = current_frame_info.total_size - offset;
         }
 
-      if (CONST_OK_FOR_I (offset))
-        emit_insn (gen_adddi3 (pic_offset_table_rtx,
-			       tmp, GEN_INT (offset)));
+      offset_r = GEN_INT (offset);
+      if (satisfies_constraint_I (offset_r))
+        emit_insn (gen_adddi3 (pic_offset_table_rtx, tmp, offset_r));
       else
         {
-          emit_move_insn (pic_offset_table_rtx, GEN_INT (offset));
+          emit_move_insn (pic_offset_table_rtx, offset_r);
           emit_insn (gen_adddi3 (pic_offset_table_rtx,
 			         pic_offset_table_rtx, tmp));
         }
@@ -2733,7 +2639,7 @@ spill_restore_mem (rtx reg, HOST_WIDE_INT cfa_off)
 
   if (spill_fill_data.prev_addr[iter])
     {
-      if (CONST_OK_FOR_N (disp))
+      if (satisfies_constraint_N (disp_rtx))
 	{
 	  *spill_fill_data.prev_addr[iter]
 	    = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter],
@@ -2747,7 +2653,7 @@ spill_restore_mem (rtx reg, HOST_WIDE_INT cfa_off)
       else
 	{
 	  /* ??? Could use register post_modify for loads.  */
-	  if (! CONST_OK_FOR_I (disp))
+	  if (!satisfies_constraint_I (disp_rtx))
 	    {
 	      rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
 	      emit_move_insn (tmp, disp_rtx);
@@ -2780,7 +2686,7 @@ spill_restore_mem (rtx reg, HOST_WIDE_INT cfa_off)
 	{
 	  start_sequence ();
 
-	  if (! CONST_OK_FOR_I (disp))
+	  if (!satisfies_constraint_I (disp_rtx))
 	    {
 	      rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
 	      emit_move_insn (tmp, disp_rtx);
@@ -3040,7 +2946,7 @@ ia64_expand_prologue (void)
       rtx frame_size_rtx = GEN_INT (- current_frame_info.total_size);
       rtx offset;
 
-      if (CONST_OK_FOR_I (- current_frame_info.total_size))
+      if (satisfies_constraint_I (frame_size_rtx))
 	offset = frame_size_rtx;
       else
 	{
@@ -3464,7 +3370,7 @@ ia64_expand_epilogue (int sibcall_p)
       rtx offset, frame_size_rtx;
 
       frame_size_rtx = GEN_INT (current_frame_info.total_size);
-      if (CONST_OK_FOR_I (current_frame_info.total_size))
+      if (satisfies_constraint_I (frame_size_rtx))
 	offset = frame_size_rtx;
       else
 	{
@@ -3572,6 +3478,7 @@ ia64_split_return_addr_rtx (rtx dest)
 	{
 	  HOST_WIDE_INT off;
 	  unsigned int regno;
+	  rtx off_r;
 
 	  /* Compute offset from CFA for BR0.  */
 	  /* ??? Must be kept in sync with ia64_expand_prologue.  */
@@ -3591,11 +3498,12 @@ ia64_split_return_addr_rtx (rtx dest)
 	    }
 
 	  /* Load address into scratch register.  */
-	  if (CONST_OK_FOR_I (off))
-	    emit_insn (gen_adddi3 (dest, src, GEN_INT (off)));
+	  off_r = GEN_INT (off);
+	  if (satisfies_constraint_I (off_r))
+	    emit_insn (gen_adddi3 (dest, src, off_r));
 	  else
 	    {
-	      emit_move_insn (dest, GEN_INT (off));
+	      emit_move_insn (dest, off_r);
 	      emit_insn (gen_adddi3 (dest, src, dest));
 	    }
 
@@ -4786,18 +4694,18 @@ ia64_rtx_costs (rtx x, int code, int outer_code, int *total)
       switch (outer_code)
         {
         case SET:
-	  *total = CONST_OK_FOR_J (INTVAL (x)) ? 0 : COSTS_N_INSNS (1);
+	  *total = satisfies_constraint_J (x) ? 0 : COSTS_N_INSNS (1);
 	  return true;
         case PLUS:
-	  if (CONST_OK_FOR_I (INTVAL (x)))
+	  if (satisfies_constraint_I (x))
 	    *total = 0;
-	  else if (CONST_OK_FOR_J (INTVAL (x)))
+	  else if (satisfies_constraint_J (x))
 	    *total = 1;
 	  else
 	    *total = COSTS_N_INSNS (1);
 	  return true;
         default:
-	  if (CONST_OK_FOR_K (INTVAL (x)) || CONST_OK_FOR_L (INTVAL (x)))
+	  if (satisfies_constraint_K (x) || satisfies_constraint_L (x))
 	    *total = 0;
 	  else
 	    *total = COSTS_N_INSNS (1);
@@ -9457,6 +9365,7 @@ ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
   rtx this, insn, funexp;
   unsigned int this_parmno;
   unsigned int this_regno;
+  rtx delta_rtx;
 
   reload_completed = 1;
   epilogue_completed = 1;
@@ -9485,25 +9394,24 @@ ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
     reg_names[this_regno] = ia64_reg_numbers[this_parmno];
 
   this = gen_rtx_REG (Pmode, this_regno);
+
+  /* Apply the constant offset, if required.  */
+  delta_rtx = GEN_INT (delta);
   if (TARGET_ILP32)
     {
       rtx tmp = gen_rtx_REG (ptr_mode, this_regno);
       REG_POINTER (tmp) = 1;
-      if (delta && CONST_OK_FOR_I (delta))
+      if (delta && satisfies_constraint_I (delta_rtx))
 	{
-	  emit_insn (gen_ptr_extend_plus_imm (this, tmp, GEN_INT (delta)));
+	  emit_insn (gen_ptr_extend_plus_imm (this, tmp, delta_rtx));
 	  delta = 0;
 	}
       else
 	emit_insn (gen_ptr_extend (this, tmp));
     }
-
-  /* Apply the constant offset, if required.  */
   if (delta)
     {
-      rtx delta_rtx = GEN_INT (delta);
-
-      if (!CONST_OK_FOR_I (delta))
+      if (!satisfies_constraint_I (delta_rtx))
 	{
 	  rtx tmp = gen_rtx_REG (Pmode, 2);
 	  emit_move_insn (tmp, delta_rtx);
@@ -9523,10 +9431,9 @@ ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
 	  rtx t = gen_rtx_REG (ptr_mode, 2);
 	  REG_POINTER (t) = 1;
 	  emit_move_insn (t, gen_rtx_MEM (ptr_mode, this));
-	  if (CONST_OK_FOR_I (vcall_offset))
+	  if (satisfies_constraint_I (vcall_offset_rtx))
 	    {
-	      emit_insn (gen_ptr_extend_plus_imm (tmp, t, 
-						  vcall_offset_rtx));
+	      emit_insn (gen_ptr_extend_plus_imm (tmp, t, vcall_offset_rtx));
 	      vcall_offset = 0;
 	    }
 	  else
@@ -9537,7 +9444,7 @@ ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
 
       if (vcall_offset)
 	{
-	  if (!CONST_OK_FOR_J (vcall_offset))
+	  if (!satisfies_constraint_J (vcall_offset_rtx))
 	    {
 	      rtx tmp2 = gen_rtx_REG (Pmode, next_scratch_gr_reg ());
 	      emit_move_insn (tmp2, vcall_offset_rtx);
@@ -9547,8 +9454,7 @@ ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
 	}
 
       if (TARGET_ILP32)
-	emit_move_insn (gen_rtx_REG (ptr_mode, 2), 
-			gen_rtx_MEM (ptr_mode, tmp));
+	emit_insn (gen_zero_extendsidi2 (tmp, gen_rtx_MEM (ptr_mode, tmp)));
       else
 	emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
 
diff --git a/gcc/config/ia64/ia64.h b/gcc/config/ia64/ia64.h
index 9e33042..951fb57 100644
--- a/gcc/config/ia64/ia64.h
+++ b/gcc/config/ia64/ia64.h
@@ -825,22 +825,6 @@ enum reg_class
    (as well as added to a displacement).  This is needed for POST_MODIFY.  */
 #define INDEX_REG_CLASS GENERAL_REGS
 
-/* A C expression which defines the machine-dependent operand constraint
-   letters for register classes.  If CHAR is such a letter, the value should be
-   the register class corresponding to it.  Otherwise, the value should be
-   `NO_REGS'.  The register letter `r', corresponding to class `GENERAL_REGS',
-   will not be passed to this macro; you do not need to handle it.  */
-
-#define REG_CLASS_FROM_LETTER(CHAR) \
-((CHAR) == 'f' ? FR_REGS		\
- : (CHAR) == 'a' ? ADDL_REGS		\
- : (CHAR) == 'b' ? BR_REGS		\
- : (CHAR) == 'c' ? PR_REGS		\
- : (CHAR) == 'd' ? AR_M_REGS		\
- : (CHAR) == 'e' ? AR_I_REGS		\
- : (CHAR) == 'x' ? FP_REGS		\
- : NO_REGS)
-
 /* A C expression which is nonzero if register number NUM is suitable for use
    as a base register in operand addresses.  It may be either a suitable hard
    register or a pseudo register that has been allocated such a hard reg.  */
@@ -905,57 +889,6 @@ enum reg_class
 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) 		\
   (SCALAR_FLOAT_MODE_P (FROM) != SCALAR_FLOAT_MODE_P (TO)	\
    ? reg_classes_intersect_p (CLASS, FR_REGS) : 0)
-
-/* A C expression that defines the machine-dependent operand constraint
-   letters (`I', `J', `K', .. 'P') that specify particular ranges of
-   integer values.  */
-
-/* 14-bit signed immediate for arithmetic instructions.  */
-#define CONST_OK_FOR_I(VALUE) \
-  ((unsigned HOST_WIDE_INT)(VALUE) + 0x2000 < 0x4000)
-/* 22-bit signed immediate for arith instructions with r0/r1/r2/r3 source.  */
-#define CONST_OK_FOR_J(VALUE) \
-  ((unsigned HOST_WIDE_INT)(VALUE) + 0x200000 < 0x400000)
-/* 8-bit signed immediate for logical instructions.  */
-#define CONST_OK_FOR_K(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x80 < 0x100)
-/* 8-bit adjusted signed immediate for compare pseudo-ops.  */
-#define CONST_OK_FOR_L(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x7F < 0x100)
-/* 6-bit unsigned immediate for shift counts.  */
-#define CONST_OK_FOR_M(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) < 0x40)
-/* 9-bit signed immediate for load/store post-increments.  */
-#define CONST_OK_FOR_N(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x100 < 0x200)
-/* 0 for r0.  Used by Linux kernel, do not change.  */
-#define CONST_OK_FOR_O(VALUE) ((VALUE) == 0)
-/* 0 or -1 for dep instruction.  */
-#define CONST_OK_FOR_P(VALUE) ((VALUE) == 0 || (VALUE) == -1)
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C) \
-  ia64_const_ok_for_letter_p (VALUE, C)
-
-/* A C expression that defines the machine-dependent operand constraint letters
-   (`G', `H') that specify particular ranges of `const_double' values.  */
-
-/* 0.0 and 1.0 for fr0 and fr1.  */
-#define CONST_DOUBLE_OK_FOR_G(VALUE) \
-  ((VALUE) == CONST0_RTX (GET_MODE (VALUE))	\
-   || (VALUE) == CONST1_RTX (GET_MODE (VALUE)))
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
-  ia64_const_double_ok_for_letter_p (VALUE, C)
-
-/* A C expression that defines the optional machine-dependent constraint
-   letters (`Q', `R', `S', `T', `U') that can be used to segregate specific
-   types of operands, usually memory references, for the target machine.  */
-
-#define EXTRA_CONSTRAINT(VALUE, C) \
-  ia64_extra_constraint (VALUE, C)
-
-/* Document the constraints that can accept reloaded memory operands.  This is
-   needed by the extended asm support, and by reload.  'Q' accepts mem, but
-   only non-volatile mem.  Since we can't reload a volatile mem into a
-   non-volatile mem, it can not be listed here.  */
-
-#define EXTRA_MEMORY_CONSTRAINT(C, STR)  ((C) == 'S')
 
 /* Basic Stack Layout */
 
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index 2704089..b9c35d6 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -101,6 +101,7 @@
   ])
 
 (include "predicates.md")
+(include "constraints.md")
 
 ;; ::::::::::::::::::::
 ;; ::
@@ -1346,9 +1347,9 @@
 (define_insn "*depz_internal"
   [(set (match_operand:DI 0 "gr_register_operand" "=r")
 	(and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r")
-			   (match_operand:DI 2 "const_int_operand" "n"))
+			   (match_operand:DI 2 "const_int_operand" "M"))
 		(match_operand:DI 3 "const_int_operand" "n")))]
-  "CONST_OK_FOR_M (INTVAL (operands[2]))
+  "satisfies_constraint_M (operands[2])
    && ia64_depz_field_mask (operands[3], operands[2]) > 0"
 {
   operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2]));
@@ -2809,7 +2810,7 @@
 	(minus:TI (match_operand:TI 1 "immediate_operand" "")
 		  (match_operand:TI 2 "register_operand" "")))
    (clobber (match_scratch:BI 3 "=&c"))]
-  "reload_completed && CONST_OK_FOR_K (INTVAL (operands[1]))"
+  "reload_completed && satisfies_constraint_K (operands[1])"
   [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))
    (set (match_dup 3) (gtu:BI (match_dup 0) (match_dup 1)))
    (cond_exec (ne (match_dup 3) (const_int 0))
diff --git a/gcc/config/ia64/predicates.md b/gcc/config/ia64/predicates.md
index 3dd5973..dbf8bb2 100644
--- a/gcc/config/ia64/predicates.md
+++ b/gcc/config/ia64/predicates.md
@@ -434,25 +434,25 @@
 (define_predicate "gr_reg_or_6bit_operand"
   (ior (match_operand 0 "gr_register_operand")
        (and (match_code "const_int")
-	    (match_test "CONST_OK_FOR_M (INTVAL (op))"))))
+	    (match_test "satisfies_constraint_M (op)"))))
 
 ;; True if OP is a GR register operand, or an 8-bit immediate operand.
 (define_predicate "gr_reg_or_8bit_operand"
   (ior (match_operand 0 "gr_register_operand")
        (and (match_code "const_int")
-	    (match_test "CONST_OK_FOR_K (INTVAL (op))"))))
+	    (match_test "satisfies_constraint_K (op)"))))
 
 ;; True if OP is a GR/FR register operand, or an 8-bit immediate operand.
 (define_predicate "grfr_reg_or_8bit_operand"
   (ior (match_operand 0 "grfr_register_operand")
        (and (match_code "const_int")
-	    (match_test "CONST_OK_FOR_K (INTVAL (op))"))))
+	    (match_test "satisfies_constraint_K (op)"))))
 
 ;; True if OP is a register operand, or an 8-bit adjusted immediate operand.
 (define_predicate "gr_reg_or_8bit_adjusted_operand"
   (ior (match_operand 0 "gr_register_operand")
        (and (match_code "const_int")
-	    (match_test "CONST_OK_FOR_L (INTVAL (op))"))))
+	    (match_test "satisfies_constraint_L (op)"))))
 
 ;; True if OP is a register operand, or is valid for both an 8-bit
 ;; immediate and an 8-bit adjusted immediate operand.  This is necessary
@@ -461,20 +461,20 @@
 (define_predicate "gr_reg_or_8bit_and_adjusted_operand"
   (ior (match_operand 0 "gr_register_operand")
        (and (match_code "const_int")
-	    (match_test "CONST_OK_FOR_K (INTVAL (op))
-                         && CONST_OK_FOR_L (INTVAL (op))"))))
+	    (match_test "satisfies_constraint_K (op)
+                         && satisfies_constraint_L (op)"))))
 
 ;; True if OP is a register operand, or a 14-bit immediate operand.
 (define_predicate "gr_reg_or_14bit_operand"
   (ior (match_operand 0 "gr_register_operand")
        (and (match_code "const_int")
-	    (match_test "CONST_OK_FOR_I (INTVAL (op))"))))
+	    (match_test "satisfies_constraint_I (op)"))))
 
 ;;  True if OP is a register operand, or a 22-bit immediate operand.
 (define_predicate "gr_reg_or_22bit_operand"
   (ior (match_operand 0 "gr_register_operand")
        (and (match_code "const_int")
-	    (match_test "CONST_OK_FOR_J (INTVAL (op))"))))
+	    (match_test "satisfies_constraint_J (op)"))))
 
 ;; True if OP is a 7-bit immediate operand.
 (define_predicate "dshift_count_operand"
@@ -484,12 +484,12 @@
 ;; True if OP is a 6-bit immediate operand.
 (define_predicate "shift_count_operand"
   (and (match_code "const_int")
-       (match_test "CONST_OK_FOR_M (INTVAL (op))")))
+       (match_test "satisfies_constraint_M (op)")))
 
 ;; True if OP-1 is a 6-bit immediate operand, used in extr instruction.
 (define_predicate "extr_len_operand"
   (and (match_code "const_int")
-       (match_test "CONST_OK_FOR_M (INTVAL (op) - 1)")))
+       (match_test "satisfies_constraint_M (GEN_INT (INTVAL (op) - 1))")))
 
 ;; True if OP is a 5-bit immediate operand.
 (define_predicate "shift_32bit_count_operand"
@@ -524,7 +524,7 @@
 (define_predicate "fr_reg_or_fp01_operand"
   (ior (match_operand 0 "fr_register_operand")
        (and (match_code "const_double")
-	    (match_test "CONST_DOUBLE_OK_FOR_G (op)"))))
+	    (match_test "satisfies_constraint_G (op)"))))
 
 ;; Like fr_reg_or_fp01_operand, but don't allow any SUBREGs.
 (define_predicate "xfreg_or_fp01_operand"