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author | John David Anglin <dave.anglin@nrc-cnrc.gc.ca> | 2004-05-31 16:10:54 +0000 |
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committer | John David Anglin <danglin@gcc.gnu.org> | 2004-05-31 16:10:54 +0000 |
commit | 1027314a211e7b0e2b05b6bd8f179c12f784517e (patch) | |
tree | 83fc3fc9690b6b85863349ffaffb0191fda5c0be /gcc | |
parent | 41fd3bac90eeedbfcc63255a1139d16b733db5f2 (diff) | |
download | gcc-1027314a211e7b0e2b05b6bd8f179c12f784517e.zip gcc-1027314a211e7b0e2b05b6bd8f179c12f784517e.tar.gz gcc-1027314a211e7b0e2b05b6bd8f179c12f784517e.tar.bz2 |
pa.md: Disable the peephole2 patterns that generate indexed floating-point stores when...
* pa.md: Disable the peephole2 patterns that generate indexed
floating-point stores when indexing is disabled.
From-SVN: r82489
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 5 | ||||
-rw-r--r-- | gcc/config/pa/pa.md | 28 |
2 files changed, 33 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 961c3bf..c639b56 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2004-05-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> + + * pa.md: Disable the peephole2 patterns that generate indexed + floating-point stores when indexing is disabled. + 2004-05-31 Gabriel Dos Reis <gdr@integrable-solutions.net> * c-pretty-print.c (pp_c_left_bracket): Make a function. diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index b88a8c0..646583c 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -2308,6 +2308,7 @@ (set (mem:SI (match_dup 0)) (match_operand:SI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2))) @@ -2324,6 +2325,7 @@ (set (mem:SI (match_dup 0)) (match_operand:SI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2))) @@ -2340,6 +2342,7 @@ (set (mem:SI (match_dup 0)) (match_operand:SI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" @@ -2357,6 +2360,7 @@ (set (mem:SI (match_dup 0)) (match_operand:SI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" @@ -2373,6 +2377,7 @@ (set (mem:SI (match_dup 0)) (match_operand:SI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[1]) && (TARGET_NO_SPACE_REGS || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2]))) @@ -2389,6 +2394,7 @@ (set (mem:SI (match_dup 0)) (match_operand:SI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[2]) && (TARGET_NO_SPACE_REGS || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2]))) @@ -2405,6 +2411,7 @@ (set (mem:SI (match_dup 0)) (match_operand:SI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[1]) && (TARGET_NO_SPACE_REGS @@ -2422,6 +2429,7 @@ (set (mem:SI (match_dup 0)) (match_operand:SI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && (TARGET_NO_SPACE_REGS @@ -3818,6 +3826,7 @@ (set (mem:DF (match_dup 0)) (match_operand:DF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2))) @@ -3834,6 +3843,7 @@ (set (mem:DF (match_dup 0)) (match_operand:DF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2))) @@ -3850,6 +3860,7 @@ (set (mem:DF (match_dup 0)) (match_operand:DF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" @@ -3867,6 +3878,7 @@ (set (mem:DF (match_dup 0)) (match_operand:DF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" @@ -3883,6 +3895,7 @@ (set (mem:DF (match_dup 0)) (match_operand:DF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[1]) && (TARGET_NO_SPACE_REGS || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2]))) @@ -3899,6 +3912,7 @@ (set (mem:DF (match_dup 0)) (match_operand:DF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[2]) && (TARGET_NO_SPACE_REGS || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2]))) @@ -3915,6 +3929,7 @@ (set (mem:DF (match_dup 0)) (match_operand:DF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[1]) && (TARGET_NO_SPACE_REGS @@ -3932,6 +3947,7 @@ (set (mem:DF (match_dup 0)) (match_operand:DF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && (TARGET_NO_SPACE_REGS @@ -4126,6 +4142,7 @@ (set (mem:DI (match_dup 0)) (match_operand:DI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" @@ -4143,6 +4160,7 @@ (set (mem:DI (match_dup 0)) (match_operand:DI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" @@ -4159,6 +4177,7 @@ (set (mem:DI (match_dup 0)) (match_operand:DI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[1]) && (TARGET_NO_SPACE_REGS @@ -4176,6 +4195,7 @@ (set (mem:DI (match_dup 0)) (match_operand:DI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && (TARGET_NO_SPACE_REGS @@ -4321,6 +4341,7 @@ (set (mem:SF (match_dup 0)) (match_operand:SF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2))) @@ -4337,6 +4358,7 @@ (set (mem:SF (match_dup 0)) (match_operand:SF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2))) @@ -4353,6 +4375,7 @@ (set (mem:SF (match_dup 0)) (match_operand:SF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" @@ -4370,6 +4393,7 @@ (set (mem:SF (match_dup 0)) (match_operand:SF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && FP_REGNO_P (REGNO (operands[3]))" @@ -4386,6 +4410,7 @@ (set (mem:SF (match_dup 0)) (match_operand:SF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[1]) && (TARGET_NO_SPACE_REGS || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2]))) @@ -4402,6 +4427,7 @@ (set (mem:SF (match_dup 0)) (match_operand:SF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[2]) && (TARGET_NO_SPACE_REGS || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2]))) @@ -4418,6 +4444,7 @@ (set (mem:SF (match_dup 0)) (match_operand:SF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[1]) && (TARGET_NO_SPACE_REGS @@ -4435,6 +4462,7 @@ (set (mem:SF (match_dup 0)) (match_operand:SF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT + && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) && (TARGET_NO_SPACE_REGS |