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| author | Kyrylo Tkachov <ktkachov@nvidia.com> | 2024-12-03 04:12:09 -0800 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@nvidia.com> | 2024-12-09 10:27:31 +0100 |
| commit | 0b79d8b98ec086fccd4714c1ff66ff4382780183 (patch) | |
| tree | 3db44f8818d4dab09caa65c1caab2bbfbc580e97 /gcc | |
| parent | 3076539544d3e36684cc8eed3374aeff5b44c9b1 (diff) | |
| download | gcc-0b79d8b98ec086fccd4714c1ff66ff4382780183.zip gcc-0b79d8b98ec086fccd4714c1ff66ff4382780183.tar.gz gcc-0b79d8b98ec086fccd4714c1ff66ff4382780183.tar.bz2 | |
aarch64: Update cpuinfo strings for some arch features
The entries for some recently-added arch features were missing the cpuinfo
string used in -march=native detection. Presumably the Linux kernel had not
specified such a string at the time the GCC support was added.
But I see that current versions of Linux do have strings for these features
in the arch/arm64/kernel/cpuinfo.c file in the kernel tree.
This patch adds them. This fixes the strings for the f32mm and f64mm features
which I think were using the wrong string. The kernel exposes them with an
"sve" prefix.
Bootstrapped and tested on aarch64-none-linux-gnu.
Signed-off-by: Kyrylo Tkachov <ktkachov@nvidia.com>
gcc/
* config/aarch64/aarch64-option-extensions.def (sve-b16b16,
f32mm, f64mm, sve2p1, sme-f64f64, sme-i16i64, sme-b16b16,
sme-f16f16, mops): Update FEATURE_STRING field.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/aarch64/aarch64-option-extensions.def | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index 52c3e7b..eb0459d 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -166,13 +166,13 @@ AARCH64_FMV_FEATURE("rpres", RPRES, ()) AARCH64_OPT_FMV_EXTENSION("sve", SVE, (SIMD, F16), (), (), "sve") /* This specifically does not imply +sve. */ -AARCH64_OPT_EXTENSION("sve-b16b16", SVE_B16B16, (), (), (), "") +AARCH64_OPT_EXTENSION("sve-b16b16", SVE_B16B16, (), (), (), "sveb16b16") -AARCH64_OPT_EXTENSION("f32mm", F32MM, (SVE), (), (), "f32mm") +AARCH64_OPT_EXTENSION("f32mm", F32MM, (SVE), (), (), "svef32mm") AARCH64_FMV_FEATURE("f32mm", SVE_F32MM, (F32MM)) -AARCH64_OPT_EXTENSION("f64mm", F64MM, (SVE), (), (), "f64mm") +AARCH64_OPT_EXTENSION("f64mm", F64MM, (SVE), (), (), "svef64mm") AARCH64_FMV_FEATURE("f64mm", SVE_F64MM, (F64MM)) @@ -195,7 +195,7 @@ AARCH64_OPT_EXTENSION("sve2-sm4", SVE2_SM4, (SVE2, SM4), (), (), "svesm4") AARCH64_FMV_FEATURE("sve2-sm4", SVE_SM4, (SVE2_SM4)) -AARCH64_OPT_EXTENSION("sve2p1", SVE2p1, (SVE2), (), (), "") +AARCH64_OPT_EXTENSION("sve2p1", SVE2p1, (SVE2), (), (), "sve2p1") AARCH64_OPT_FMV_EXTENSION("sme", SME, (BF16, SVE2), (), (), "sme") @@ -215,11 +215,11 @@ AARCH64_OPT_EXTENSION("pauth", PAUTH, (), (), (), "paca pacg") AARCH64_OPT_EXTENSION("ls64", LS64, (), (), (), "") -AARCH64_OPT_EXTENSION("sme-f64f64", SME_F64F64, (SME), (), (), "") +AARCH64_OPT_EXTENSION("sme-f64f64", SME_F64F64, (SME), (), (), "smef64f64") AARCH64_FMV_FEATURE("sme-f64f64", SME_F64, (SME_F64F64)) -AARCH64_OPT_EXTENSION("sme-i16i64", SME_I16I64, (SME), (), (), "") +AARCH64_OPT_EXTENSION("sme-i16i64", SME_I16I64, (SME), (), (), "smei16i64") AARCH64_FMV_FEATURE("sme-i16i64", SME_I64, (SME_I16I64)) @@ -227,11 +227,11 @@ AARCH64_OPT_FMV_EXTENSION("sme2", SME2, (SME), (), (), "sme2") AARCH64_OPT_EXTENSION("sme2p1", SME2p1, (SME2), (), (), "sme2p1") -AARCH64_OPT_EXTENSION("sme-b16b16", SME_B16B16, (SME2, SVE_B16B16), (), (), "") +AARCH64_OPT_EXTENSION("sme-b16b16", SME_B16B16, (SME2, SVE_B16B16), (), (), "smeb16b16") -AARCH64_OPT_EXTENSION("sme-f16f16", SME_F16F16, (SME2), (), (), "") +AARCH64_OPT_EXTENSION("sme-f16f16", SME_F16F16, (SME2), (), (), "smef16f16") -AARCH64_OPT_EXTENSION("mops", MOPS, (), (), (), "") +AARCH64_OPT_EXTENSION("mops", MOPS, (), (), (), "mops") AARCH64_OPT_EXTENSION("cssc", CSSC, (), (), (), "cssc") |