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| author | Alan Lawrence <alan.lawrence@arm.com> | 2014-11-24 15:23:28 +0000 |
|---|---|---|
| committer | Alan Lawrence <alalaw01@gcc.gnu.org> | 2014-11-24 15:23:28 +0000 |
| commit | 0b4eefd5a8b3b626915cbd49ac7d956424c8b467 (patch) | |
| tree | ad9130dd31daa673cdc7feb9dc3758de07041c8b /gcc | |
| parent | d9e80f4944deb243a8771917236d49c434c029ef (diff) | |
| download | gcc-0b4eefd5a8b3b626915cbd49ac7d956424c8b467.zip gcc-0b4eefd5a8b3b626915cbd49ac7d956424c8b467.tar.gz gcc-0b4eefd5a8b3b626915cbd49ac7d956424c8b467.tar.bz2 | |
[AArch64]Add vec_shr pattern for 64-bit vectors using ush{l,r}; enable tests.
gcc/:
* config/aarch64/aarch64-simd.md (vec_shr<mode>): New.
gcc/testsuite/:
* lib/target-supports.exp (check_effective_target_whole_vector_shift):
Add aarch64{,_be}.
From-SVN: r218022
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 15 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/lib/target-supports.exp | 1 |
4 files changed, 25 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f1171a7..ee51e9b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2014-11-24 Alan Lawrence <alan.lawrence@arm.com> + * config/aarch64/aarch64-simd.md (vec_shr<mode>): New. + +2014-11-24 Alan Lawrence <alan.lawrence@arm.com> + * config/aarch64/aarch64-builtins.c (aarch64_simd_expand_args): Refactor by combining switch statements and make arrays into scalars. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index eed01cf..8e31456 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -795,6 +795,21 @@ } ) +;; For 64-bit modes we use ushl/r, as this does not require a SIMD zero. +(define_insn "vec_shr_<mode>" + [(set (match_operand:VD 0 "register_operand" "=w") + (lshiftrt:VD (match_operand:VD 1 "register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")))] + "TARGET_SIMD" + { + if (BYTES_BIG_ENDIAN) + return "ushl %d0, %d1, %2"; + else + return "ushr %d0, %d1, %2"; + } + [(set_attr "type" "neon_shift_imm")] +) + (define_insn "aarch64_simd_vec_setv2di" [(set (match_operand:V2DI 0 "register_operand" "=w,w") (vec_merge:V2DI diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 7db895b..e673893 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2014-11-24 Alan Lawrence <alan.lawrence@arm.com> + + * lib/target-supports.exp (check_effective_target_whole_vector_shift): + Add aarch64{,_be}. + 2014-11-24 Richard Biener <rguenther@suse.de> PR tree-optimization/63679 diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 02b2b77..ac04d95 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -3399,6 +3399,7 @@ proc check_effective_target_vect_shift { } { proc check_effective_target_whole_vector_shift { } { if { [istarget i?86-*-*] || [istarget x86_64-*-*] || [istarget ia64-*-*] + || [istarget aarch64*-*-*] || ([check_effective_target_arm32] && [check_effective_target_arm_little_endian]) || ([istarget mips*-*-*] |