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| author | Ian Bolton <ian.bolton@arm.com> | 2013-04-29 16:13:16 +0000 |
|---|---|---|
| committer | Ian Bolton <ibolton@gcc.gnu.org> | 2013-04-29 16:13:16 +0000 |
| commit | 0b064172a207fb1663bcba23513a11c1be1c5edc (patch) | |
| tree | c30058bc57408b7bf0e1f8aa67728e6b81b4e997 /gcc | |
| parent | 473cec554a78fc340c970493000ebd14f74511db (diff) | |
| download | gcc-0b064172a207fb1663bcba23513a11c1be1c5edc.zip gcc-0b064172a207fb1663bcba23513a11c1be1c5edc.tar.gz gcc-0b064172a207fb1663bcba23513a11c1be1c5edc.tar.bz2 | |
[AArch64] Support LDR/STR from/to S and D registers
From-SVN: r198425
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 20 |
2 files changed, 18 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9f09e14..de4db3f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2013-04-29 Ian Bolton <ian.bolton@arm.com> + * config/aarch64/aarch64.md (movsi_aarch64): Support LDR/STR + from/to S register. + (movdi_aarch64): Support LDR/STR from/to D register. + +2013-04-29 Ian Bolton <ian.bolton@arm.com> + * common/config/aarch64/aarch64-common.c: Enable REE pass at O2 or higher by default. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 963c9ca..87e68fa 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -809,26 +809,28 @@ ) (define_insn "*movsi_aarch64" - [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m, *w, r,*w") - (match_operand:SI 1 "aarch64_mov_operand" " r,M,m,rZ,rZ,*w,*w"))] + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,*w,m, m,*w, r,*w") + (match_operand:SI 1 "aarch64_mov_operand" " r,M,m, m,rZ,*w,rZ,*w,*w"))] "(register_operand (operands[0], SImode) || aarch64_reg_or_zero (operands[1], SImode))" "@ mov\\t%w0, %w1 mov\\t%w0, %1 ldr\\t%w0, %1 + ldr\\t%s0, %1 str\\t%w1, %0 + str\\t%s1, %0 fmov\\t%s0, %w1 fmov\\t%w0, %s1 fmov\\t%s0, %s1" - [(set_attr "v8type" "move,alu,load1,store1,fmov,fmov,fmov") + [(set_attr "v8type" "move,alu,load1,load1,store1,store1,fmov,fmov,fmov") (set_attr "mode" "SI") - (set_attr "fp" "*,*,*,*,yes,yes,yes")] + (set_attr "fp" "*,*,*,*,*,*,yes,yes,yes")] ) (define_insn "*movdi_aarch64" - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,k,r,r,r,m, r, r, *w, r,*w,w") - (match_operand:DI 1 "aarch64_mov_operand" " r,r,k,N,m,rZ,Usa,Ush,rZ,*w,*w,Dd"))] + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,k,r,r,r,*w,m, m,r, r, *w, r,*w,w") + (match_operand:DI 1 "aarch64_mov_operand" " r,r,k,N,m, m,rZ,*w,Usa,Ush,rZ,*w,*w,Dd"))] "(register_operand (operands[0], DImode) || aarch64_reg_or_zero (operands[1], DImode))" "@ @@ -837,16 +839,18 @@ mov\\t%x0, %1 mov\\t%x0, %1 ldr\\t%x0, %1 + ldr\\t%d0, %1 str\\t%x1, %0 + str\\t%d1, %0 adr\\t%x0, %a1 adrp\\t%x0, %A1 fmov\\t%d0, %x1 fmov\\t%x0, %d1 fmov\\t%d0, %d1 movi\\t%d0, %1" - [(set_attr "v8type" "move,move,move,alu,load1,store1,adr,adr,fmov,fmov,fmov,fmov") + [(set_attr "v8type" "move,move,move,alu,load1,load1,store1,store1,adr,adr,fmov,fmov,fmov,fmov") (set_attr "mode" "DI") - (set_attr "fp" "*,*,*,*,*,*,*,*,yes,yes,yes,yes")] + (set_attr "fp" "*,*,*,*,*,*,*,*,*,*,yes,yes,yes,yes")] ) (define_insn "insv_imm<mode>" |