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| author | Palmer Dabbelt <palmer@rivosinc.com> | 2023-05-11 15:28:49 -0700 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2023-08-31 20:45:01 +0800 |
| commit | 0337555c7a2524bd334bafdc06dd801818eb34b6 (patch) | |
| tree | f5b9fa3887677dd5ee87ca6609653f458399f6cc /gcc | |
| parent | 4da3065a6422062b029df9660a226297802455f4 (diff) | |
| download | gcc-0337555c7a2524bd334bafdc06dd801818eb34b6.zip gcc-0337555c7a2524bd334bafdc06dd801818eb34b6.tar.gz gcc-0337555c7a2524bd334bafdc06dd801818eb34b6.tar.bz2 | |
RISC-V: Add vector_scalar_shift_operand
The vector shift immediates happen to have the same constraints as some
of the CSR-related operands, but it's a different usage. This adds a
name for them, so I don't get confused again next time.
gcc/ChangeLog:
* config/riscv/autovec.md (shifts): Use
vector_scalar_shift_operand.
* config/riscv/predicates.md (vector_scalar_shift_operand): New
predicate.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/autovec.md | 6 | ||||
| -rw-r--r-- | gcc/config/riscv/predicates.md | 5 |
2 files changed, 8 insertions, 3 deletions
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 3e0a1da..4f6fbf5 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -440,10 +440,10 @@ ;; ------------------------------------------------------------------------- (define_insn_and_split "<optab><mode>3" - [(set (match_operand:V_VLSI 0 "register_operand" "=vr") + [(set (match_operand:V_VLSI 0 "register_operand" "=vr") (any_shift:V_VLSI - (match_operand:V_VLSI 1 "register_operand" " vr") - (match_operand:<VEL> 2 "csr_operand" " rK")))] + (match_operand:V_VLSI 1 "register_operand" " vr") + (match_operand:<VEL> 2 "vector_scalar_shift_operand" " rK")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 3be87df..53e7c1d 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -49,6 +49,11 @@ (ior (match_operand 0 "const_csr_operand") (match_operand 0 "register_operand"))) +;; V has 32-bit unsigned immediates. This happens to be the same constraint as +;; the csr_operand, but it's not CSR related. +(define_predicate "vector_scalar_shift_operand" + (match_operand 0 "csr_operand")) + (define_predicate "sle_operand" (and (match_code "const_int") (match_test "SMALL_OPERAND (INTVAL (op) + 1)"))) |