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authorJoseph Myers <joseph@codesourcery.com>2011-03-30 11:01:13 +0100
committerRainer Orth <ro@gcc.gnu.org>2011-03-30 10:01:13 +0000
commit023592aa3be2da79c9194fcf60a2ac395fede455 (patch)
tree84653b4650d78c739723ea3d300049ebeab35ac6 /gcc
parent5453bbef09e7c3afb3aa0227e99d225d055f90cb (diff)
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re PR bootstrap/48337 (options.c doesn't compile on SPARC)
2011-03-30 Joseph Myers <joseph@codesourcery.com> Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> PR bootstrap/48337 * config/sparc/sparc.opt (sparc_cpu_and_features): Add Init(PROCESSOR_V7). (sparc_cpu): Likewise. * config/sparc/sparc.c (sparc_option_override): Replace 0 by PROCESSOR_V7. Co-Authored-By: Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> From-SVN: r171717
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog10
-rw-r--r--gcc/config/sparc/sparc.c2
-rw-r--r--gcc/config/sparc/sparc.opt4
3 files changed, 13 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 689f291..cd95c4a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2011-03-30 Joseph Myers <joseph@codesourcery.com>
+ Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
+
+ PR bootstrap/48337
+ * config/sparc/sparc.opt (sparc_cpu_and_features): Add
+ Init(PROCESSOR_V7).
+ (sparc_cpu): Likewise.
+ * config/sparc/sparc.c (sparc_option_override): Replace 0 by
+ PROCESSOR_V7.
+
2011-03-29 Vladimir Makarov <vmakarov@redhat.com>
PR target/48336
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index a90cdb3..1e7ce53 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -695,7 +695,7 @@ sparc_option_override (void)
{ TARGET_CPU_ultrasparc3, PROCESSOR_ULTRASPARC3 },
{ TARGET_CPU_niagara, PROCESSOR_NIAGARA },
{ TARGET_CPU_niagara2, PROCESSOR_NIAGARA2 },
- { -1, 0 }
+ { -1, PROCESSOR_V7 }
};
const struct cpu_default *def;
/* Table of values for -m{cpu,tune}=. This must match the order of
diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt
index 9d8e26b..b7fac09 100644
--- a/gcc/config/sparc/sparc.opt
+++ b/gcc/config/sparc/sparc.opt
@@ -86,11 +86,11 @@ Target
Optimize tail call instructions in assembler and linker
mcpu=
-Target RejectNegative Joined Var(sparc_cpu_and_features) Enum(sparc_processor_type)
+Target RejectNegative Joined Var(sparc_cpu_and_features) Enum(sparc_processor_type) Init(PROCESSOR_V7)
Use features of and schedule code for given CPU
mtune=
-Target RejectNegative Joined Var(sparc_cpu) Enum(sparc_processor_type)
+Target RejectNegative Joined Var(sparc_cpu) Enum(sparc_processor_type) Init(PROCESSOR_V7)
Schedule code for given CPU
Enum