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| author | Jim Wilson <jimw@sifive.com> | 2018-07-03 00:19:59 +0000 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 2018-07-02 17:19:59 -0700 |
| commit | eb153f07b3618de080b778ffff5693d94bf785b4 (patch) | |
| tree | 8a29dee6b528506ea18bad07097a888d7bca653d /gcc | |
| parent | ccf266dbb86620ae8d8ff3b1aefdea45b5524d2a (diff) | |
| download | gcc-eb153f07b3618de080b778ffff5693d94bf785b4.zip gcc-eb153f07b3618de080b778ffff5693d94bf785b4.tar.gz gcc-eb153f07b3618de080b778ffff5693d94bf785b4.tar.bz2 | |
RISC-V: Fix interrupt support for -g.
gcc/
* config/riscv/riscv.c (riscv_expand_epilogue): Use emit_jump_insn
instead of emit_insn for interrupt returns.
* config/riscv/riscv.md (riscv_met): Add (return) to rtl.
(riscv_sret, riscv_uret): Likewise.
gcc/testsuite/
* gcc.target/riscv/interrupt-debug.c: New.
From-SVN: r262327
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.c | 6 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.md | 9 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/interrupt-debug.c | 15 |
5 files changed, 35 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e0b5c65..a8c2629 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2018-07-02 Jim Wilson <jimw@sifive.com> + + * config/riscv/riscv.c (riscv_expand_epilogue): Use emit_jump_insn + instead of emit_insn for interrupt returns. + * config/riscv/riscv.md (riscv_met): Add (return) to rtl. + (riscv_sret, riscv_uret): Likewise. + 2018-07-02 David Malcolm <dmalcolm@redhat.com> * pretty-print.c (selftest::test_pp_format): Move save and restore diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 2709ebd..d87836f 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -3985,11 +3985,11 @@ riscv_expand_epilogue (int style) enum riscv_privilege_levels mode = cfun->machine->interrupt_mode; if (mode == MACHINE_MODE) - emit_insn (gen_riscv_mret ()); + emit_jump_insn (gen_riscv_mret ()); else if (mode == SUPERVISOR_MODE) - emit_insn (gen_riscv_sret ()); + emit_jump_insn (gen_riscv_sret ()); else - emit_insn (gen_riscv_uret ()); + emit_jump_insn (gen_riscv_uret ()); } else if (style != SIBCALL_RETURN) emit_jump_insn (gen_simple_return_internal (ra)); diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 7b411f0..613af9d 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2328,17 +2328,20 @@ "fsflags\t%0") (define_insn "riscv_mret" - [(unspec_volatile [(const_int 0)] UNSPECV_MRET)] + [(return) + (unspec_volatile [(const_int 0)] UNSPECV_MRET)] "" "mret") (define_insn "riscv_sret" - [(unspec_volatile [(const_int 0)] UNSPECV_SRET)] + [(return) + (unspec_volatile [(const_int 0)] UNSPECV_SRET)] "" "sret") (define_insn "riscv_uret" - [(unspec_volatile [(const_int 0)] UNSPECV_URET)] + [(return) + (unspec_volatile [(const_int 0)] UNSPECV_URET)] "" "uret") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index f2485db..fb4422f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2018-07-02 Jim Wilson <jimw@sifive.com> + + * gcc.target/riscv/interrupt-debug.c: New. + 2018-07-02 Paolo Carlini <paolo.carlini@oracle.com> * g++.dg/diagnostic/thread-thread_local.C: New. diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-debug.c b/gcc/testsuite/gcc.target/riscv/interrupt-debug.c new file mode 100644 index 0000000..a1b6dac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/interrupt-debug.c @@ -0,0 +1,15 @@ +/* Verify that we can compile with debug info. */ +/* { dg-do compile } */ +/* { dg-options "-Og -g" } */ +extern int var1; +extern int var2; +extern void sub2 (void); + +void __attribute__ ((interrupt)) +sub (void) +{ + if (var1) + var2 = 0; + else + sub2 (); +} |