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| author | Eric Botcazou <ebotcazou@adacore.com> | 2021-03-10 12:02:14 +0100 |
|---|---|---|
| committer | Eric Botcazou <ebotcazou@adacore.com> | 2021-03-10 12:32:03 +0100 |
| commit | da7343a6f48c6813a29640fec744b0a236b6540f (patch) | |
| tree | e64e9e6be913d8c90467b51b6cf8328562552491 /gcc | |
| parent | e7afb82c358855510aa90ae9869663b614a732cb (diff) | |
| download | gcc-da7343a6f48c6813a29640fec744b0a236b6540f.zip gcc-da7343a6f48c6813a29640fec744b0a236b6540f.tar.gz gcc-da7343a6f48c6813a29640fec744b0a236b6540f.tar.bz2 | |
Fix miscompilation of Ada runtime on 64-bit SPARC
Returning a REGMODE_NATURAL_SIZE of 4 for DFmode in 64-bit mode is
just asking for trouble because sub-word SUBREGs are always treated
differently than the others, in particular by the register allocator.
gcc/
* config/sparc/sparc.c (sparc_regmode_natural_size): Return 4 for
float and vector integer modes only if the mode is not larger.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/sparc/sparc.c | 15 |
1 files changed, 5 insertions, 10 deletions
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index f355793..f150417 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -13585,23 +13585,18 @@ sparc_expand_vcond (machine_mode mode, rtx *operands, int ccode, int fcode) emit_insn (gen_rtx_SET (operands[0], bshuf)); } -/* On sparc, any mode which naturally allocates into the float +/* On the SPARC, any mode which naturally allocates into the single float registers should return 4 here. */ unsigned int sparc_regmode_natural_size (machine_mode mode) { - int size = UNITS_PER_WORD; + const enum mode_class cl = GET_MODE_CLASS (mode); - if (TARGET_ARCH64) - { - enum mode_class mclass = GET_MODE_CLASS (mode); - - if (mclass == MODE_FLOAT || mclass == MODE_VECTOR_INT) - size = 4; - } + if ((cl == MODE_FLOAT || cl == MODE_VECTOR_INT) && GET_MODE_SIZE (mode) <= 4) + return 4; - return size; + return UNITS_PER_WORD; } /* Implement TARGET_HARD_REGNO_NREGS. |