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| author | H.J. Lu <hongjiu.lu@intel.com> | 2016-04-20 19:45:49 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2016-04-20 12:45:49 -0700 |
| commit | dda49daffdfdbb10768cd4b89c7c349d3dd45415 (patch) | |
| tree | 300a821862e0cd4efcf2c32c8e42fbe2b881bc06 /gcc | |
| parent | 8a5b9d5a9934a14a38f67c9b389c46ec062b98cd (diff) | |
| download | gcc-dda49daffdfdbb10768cd4b89c7c349d3dd45415.zip gcc-dda49daffdfdbb10768cd4b89c7c349d3dd45415.tar.gz gcc-dda49daffdfdbb10768cd4b89c7c349d3dd45415.tar.bz2 | |
Add -mtune-ctrl=sse_typeless_stores to avx256-unaligned-store-2.c
Since avx256-unaligned-store-2.c scans typeless SSE stores, add
-mtune-ctrl=sse_typeless_stores to enable typeless SSE stores.
* gcc.target/i386/avx256-unaligned-store-2.c: Add
-mtune-ctrl=sse_typeless_stores.
From-SVN: r235296
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c | 2 |
2 files changed, 6 insertions, 1 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a9dc717..1bb9411 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,10 @@ 2016-04-20 H.J. Lu <hongjiu.lu@intel.com> + * gcc.target/i386/avx256-unaligned-store-2.c: Add + -mtune-ctrl=sse_typeless_stores. + +2016-04-20 H.J. Lu <hongjiu.lu@intel.com> + * gcc.target/i386/avx256-unaligned-load-1.c: Update load scan. 2016-04-20 Bin Cheng <bin.cheng@arm.com> diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c index 817be17..87285c6 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { ! ia32 } } } */ -/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-store -mno-prefer-avx128" } */ +/* { dg-options "-O3 -mtune-ctrl=sse_typeless_stores -dp -mavx -mavx256-split-unaligned-store -mno-prefer-avx128" } */ #define N 1024 |