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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-09-14 15:54:37 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-09-14 15:56:56 +0800 |
| commit | 7c4f6ebe54f4da0097acd07f41782ff6cc39e9a4 (patch) | |
| tree | 6834d9070e4527f0b362f1619cdf5bdf95fa1215 /gcc | |
| parent | 3acf7e9da39360dab6ebb9dfc92208e9dadd982a (diff) | |
| download | gcc-7c4f6ebe54f4da0097acd07f41782ff6cc39e9a4.zip gcc-7c4f6ebe54f4da0097acd07f41782ff6cc39e9a4.tar.gz gcc-7c4f6ebe54f4da0097acd07f41782ff6cc39e9a4.tar.bz2 | |
RISC-V: Format VSETVL PASS code
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::global_eliminate_vsetvl_insn): Format it.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv-vsetvl.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index f81361c..e9e75fe 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -4054,7 +4054,8 @@ pass_vsetvl::global_eliminate_vsetvl_insn (const bb_info *bb) const } /* Step1: Reshape the VL/VTYPE status to make sure everything compatible. */ - auto_vec<basic_block> pred_cfg_bbs = get_dominated_by (CDI_POST_DOMINATORS, cfg_bb); + auto_vec<basic_block> pred_cfg_bbs + = get_dominated_by (CDI_POST_DOMINATORS, cfg_bb); FOR_EACH_EDGE (e, ei, cfg_bb->preds) { sbitmap avout = m_vector_manager->vector_avout[e->src->index]; |