From 7c4f6ebe54f4da0097acd07f41782ff6cc39e9a4 Mon Sep 17 00:00:00 2001
From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Thu, 14 Sep 2023 15:54:37 +0800
Subject: RISC-V: Format VSETVL PASS code

gcc/ChangeLog:

	* config/riscv/riscv-vsetvl.cc (pass_vsetvl::global_eliminate_vsetvl_insn): Format it.
---
 gcc/config/riscv/riscv-vsetvl.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'gcc')

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index f81361c..e9e75fe 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -4054,7 +4054,8 @@ pass_vsetvl::global_eliminate_vsetvl_insn (const bb_info *bb) const
     }
 
   /* Step1: Reshape the VL/VTYPE status to make sure everything compatible.  */
-  auto_vec<basic_block> pred_cfg_bbs = get_dominated_by (CDI_POST_DOMINATORS, cfg_bb);
+  auto_vec<basic_block> pred_cfg_bbs
+    = get_dominated_by (CDI_POST_DOMINATORS, cfg_bb);
   FOR_EACH_EDGE (e, ei, cfg_bb->preds)
     {
       sbitmap avout = m_vector_manager->vector_avout[e->src->index];
-- 
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