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| author | Xi Ruoyao <xry111@xry111.site> | 2025-02-13 22:51:31 +0800 |
|---|---|---|
| committer | Xi Ruoyao <xry111@xry111.site> | 2025-02-19 14:34:46 +0800 |
| commit | 427386042f056a2910882bf0c632b4db68c52bbb (patch) | |
| tree | db3b8c138c915c02032073e8d0f424844bb758e2 /gcc/tree-vect-loop.cc | |
| parent | cef5f23adb6f9f052d03286ad8ccf352eefccf86 (diff) | |
| download | gcc-427386042f056a2910882bf0c632b4db68c52bbb.zip gcc-427386042f056a2910882bf0c632b4db68c52bbb.tar.gz gcc-427386042f056a2910882bf0c632b4db68c52bbb.tar.bz2 | |
LoongArch: Use normal RTL pattern instead of UNSPEC for {x,}vsr{a,l}ri instructions
Allowing (t + (1ul << imm >> 1)) >> imm to be recognized as a rounding
shift operation.
gcc/ChangeLog:
* config/loongarch/lasx.md (UNSPEC_LASX_XVSRARI): Remove.
(UNSPEC_LASX_XVSRLRI): Remove.
(lasx_xvsrari_<lsxfmt>): Remove.
(lasx_xvsrlri_<lsxfmt>): Remove.
* config/loongarch/lsx.md (UNSPEC_LSX_VSRARI): Remove.
(UNSPEC_LSX_VSRLRI): Remove.
(lsx_vsrari_<lsxfmt>): Remove.
(lsx_vsrlri_<lsxfmt>): Remove.
* config/loongarch/simd.md (simd_<optab>_imm_round_<mode>): New
define_insn.
(<simd_isa>_<x>v<insn>ri_<simdfmt>): New define_expand.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/vect-shift-imm-round.c: New test.
Diffstat (limited to 'gcc/tree-vect-loop.cc')
0 files changed, 0 insertions, 0 deletions