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| author | Jeff Law <jlaw@ventanamicro.com> | 2024-08-25 07:24:56 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2024-08-25 07:24:56 -0600 |
| commit | 70edccf88738ec204036e498a4a50c46e5e4f0c0 (patch) | |
| tree | 0dfdf5e76fd286fd244bedc0ada39c81cd63b3a9 /gcc/tree-ssa-loop-im.cc | |
| parent | 4c3485897d3e28ecfbe911f21f83fa047ee8b54b (diff) | |
| download | gcc-70edccf88738ec204036e498a4a50c46e5e4f0c0.zip gcc-70edccf88738ec204036e498a4a50c46e5e4f0c0.tar.gz gcc-70edccf88738ec204036e498a4a50c46e5e4f0c0.tar.bz2 | |
Disable late-combine in another RISC-V test
Another test where the output was slightly twiddled by late-combine in which
simply disabling late-combine seems to be the best option.
> Running /home/jlaw/test/gcc/gcc/testsuite/gcc.target/riscv/riscv.exp ...
> FAIL: gcc.target/riscv/cm_mv_rv32.c -Os check-function-bodies sum
Pushing to the trunk.
gcc/testsuite
* gcc.target/riscv/cm_mv_rv32.c: Disable late-combine.
Diffstat (limited to 'gcc/tree-ssa-loop-im.cc')
0 files changed, 0 insertions, 0 deletions