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| author | Richard Biener <rguenther@suse.de> | 2025-03-27 08:40:32 +0100 |
|---|---|---|
| committer | Richard Biener <rguenth@gcc.gnu.org> | 2025-03-27 14:31:55 +0100 |
| commit | 088ed1042d12f23261bc499b927b93fd61f8d574 (patch) | |
| tree | ded0b7d60a1f0a03fb42be9a6057ff5e096fff90 /gcc/tree-ssa-loop-im.cc | |
| parent | 365c82dbf3319e5adb5cced2dae0c4a9aa48f5bc (diff) | |
| download | gcc-088ed1042d12f23261bc499b927b93fd61f8d574.zip gcc-088ed1042d12f23261bc499b927b93fd61f8d574.tar.gz gcc-088ed1042d12f23261bc499b927b93fd61f8d574.tar.bz2 | |
target/119010 - add znver{4,5}_insn_both to resolve missing reservations
I still was seeing
;; 0--> b 0: i 101 {[sp-0x3c]=[sp-0x3c]+0x1;clobber flags;}:nothing
so the following adds a standard alu insn reservation mimicing that
from the znver.md description allowing both load and store.
PR target/119010
* config/i386/zn4zn5.md (znver4_insn_both, znver5_insn_both):
New reservation for ALU ops with load and store.
Diffstat (limited to 'gcc/tree-ssa-loop-im.cc')
0 files changed, 0 insertions, 0 deletions