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| author | Jakub Jelinek <jakub@redhat.com> | 2023-11-24 12:12:20 +0100 |
|---|---|---|
| committer | Jakub Jelinek <jakub@redhat.com> | 2023-11-24 12:13:07 +0100 |
| commit | 3eb9cae6d375d222787498b15ac87f383b3834fe (patch) | |
| tree | a0051f2849d128d3bb8c57486593a8e371b36495 /gcc/tree-ssa-ifcombine.cc | |
| parent | fea27dfd227c49f1409260e814e400fce4fbe2a7 (diff) | |
| download | gcc-3eb9cae6d375d222787498b15ac87f383b3834fe.zip gcc-3eb9cae6d375d222787498b15ac87f383b3834fe.tar.gz gcc-3eb9cae6d375d222787498b15ac87f383b3834fe.tar.bz2 | |
i386: Fix ICE during cbranchv16qi4 expansion [PR112681]
The following testcase ICEs, because cbranchv16qi4 expansion calls
ix86_expand_branch with op1 being a pre-AVX unaligned memory and
ix86_expand_branch emits a xorv16qi3 instruction without making sure
the operand predicates are satisfied.
While I could manually check if the argument (or both?) doesn't
match vector_operand predicate (apparently this one or bcst_vector_operand
is used in all integral 16+ bytes *xorv*3 instructions) force it into a
register, but as all gen_xorv*3 expanders call
ix86_expand_vector_logical_operator, it seems easier to just call that
function which ensures the right thing happens. Calling the individual
gen_xorv*3 functions would mean ugly switch on the modes and using high
level expand_simple_binop here seems too high level to me.
2023-11-24 Jakub Jelinek <jakub@redhat.com>
PR target/112681
* config/i386/i386-expand.cc (ix86_expand_branch): Use
ix86_expand_vector_logical_operator to expand vector XOR rather than
gen_rtx_SET on gen_rtx_XOR.
* gcc.target/i386/sse4-pr112681.c: New test.
Diffstat (limited to 'gcc/tree-ssa-ifcombine.cc')
0 files changed, 0 insertions, 0 deletions