[RISC-V][PR target/106544] Avoid ICEs due to bogus asms

This is a fix for a bug Andrew P filed a while back where essentially a poorly
crafted asm statement could trigger a ICE during assembly output.  Various
cases will use INTVAL (op) without verifying the operand is a CONST_INT node
first.

The usual way to handle this is via output_operand_lossage, which this patch
implements.

I focused primarily on the CONST_INT cases, there could well be other problems
in this space, if so they should get distinct bugs with testcases.

Tested in my tester on rv32 and rv64.  Waiting for pre-commit testing before
moving forward.

	PR target/106544
gcc/

	* config/riscv/riscv.cc (riscv_print_operand): Issue an error for
	invalid operands rather than invalidly accessing INTVAL of an
	object that is not a CONST_INT.  Fix one error string for 'N'.

gcc/testsuite
	* gcc.target/riscv/pr106544.c: New test.

0 files changed, 0 insertions, 0 deletions