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| author | Anton Blanchard <antonb@tenstorrent.com> | 2024-12-17 07:34:20 -0700 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2024-12-17 07:35:00 -0700 |
| commit | 4aa01ecc5c1389d1cdf5721b936993ba17b96178 (patch) | |
| tree | bd6db66efbfeab53d7020e751640c0b98a7547bd /gcc/tree-inline.h | |
| parent | 5601c411f4ffdb8bbfec09a58234ab2ebc5de986 (diff) | |
| download | gcc-4aa01ecc5c1389d1cdf5721b936993ba17b96178.zip gcc-4aa01ecc5c1389d1cdf5721b936993ba17b96178.tar.gz gcc-4aa01ecc5c1389d1cdf5721b936993ba17b96178.tar.bz2 | |
[PATCH v2 2/2] RISC-V: Add Tenstorrent Ascalon 8 wide architecture
This adds the Tenstorrent Ascalon 8 wide architecture (tt-ascalon-d8)
to the list of known cores.
gcc/ChangeLog:
* config/riscv/riscv-cores.def: Add tt-ascalon-d8.
* config/riscv/riscv.cc (tt_ascalon_d8_tune_info): New.
* doc/invoke.texi (RISC-V): Add tt-ascalon-d8 to -mcpu.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/mcpu-tt-ascalon-d8.c: New test.
Diffstat (limited to 'gcc/tree-inline.h')
0 files changed, 0 insertions, 0 deletions