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author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-05-15 22:23:45 +0800 |
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committer | Pan Li <pan2.li@intel.com> | 2023-05-15 22:23:45 +0800 |
commit | 5ed880788ba33302de5d78574464201e0fecbc70 (patch) | |
tree | d8b89f02099ddd5e05bf712ba93d26fbefad9e66 /gcc/tree-data-ref.h | |
parent | 47c4e96ad61a19ec3adb39587bf0d7d0b51a51b3 (diff) | |
download | gcc-5ed880788ba33302de5d78574464201e0fecbc70.zip gcc-5ed880788ba33302de5d78574464201e0fecbc70.tar.gz gcc-5ed880788ba33302de5d78574464201e0fecbc70.tar.bz2 |
RISC-V: Add rounding mode operand for fixed-point patterns
Since we are going to have fixed-point intrinsics that are modeling
rounding mode
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222
We should have operand to specify rounding mode in fixed-point instructions.
We don't support these modeling rounding mode intrinsics yet but we will
definetely support them later.
This is the preparing patch for new coming intrinsics.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (enum vxrm_field_enum): New enum.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_exact_insn): Add default rounding mode operand.
* config/riscv/riscv.cc (riscv_hard_regno_nregs): Add VXRM_REGNUM.
(riscv_hard_regno_mode_ok): Ditto.
(riscv_conditional_register_usage): Ditto.
* config/riscv/riscv.h (DWARF_FRAME_REGNUM): Ditto.
(VXRM_REG_P): Ditto.
(RISCV_DWARF_VXRM): Ditto.
* config/riscv/riscv.md: Ditto.
* config/riscv/vector.md: Ditto
Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Diffstat (limited to 'gcc/tree-data-ref.h')
0 files changed, 0 insertions, 0 deletions