RISC-V: Handle overlap in expand_vec_perm PR121742.

In a two-source gather we unconditionally overwrite target with the
first gather's result already.  If op1 == target this clobbers the
source operand for the second gather.  This patch uses a temporary in
that case.

	PR target/121742

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (expand_vec_perm): Use temporary if
	op1 and target overlap.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/pr121742.c: New test.

1 files changed, 30 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121742.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121742.c
new file mode 100644
index 0000000..08491f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121742.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */
+
+typedef unsigned long uint64_t;
+typedef unsigned int uint32_t;
+typedef unsigned char uint8_t;
+typedef uint8_t a __attribute__((vector_size(4)));
+int b, c;
+
+uint64_t d() {
+  a e = {5, 9, 1, 5};
+  a bla = {0, 0, 0, 0};
+  int *f = &b;
+  uint32_t g = 0;
+  int i = 0;
+  for (; i < 2; i++)
+    for (c = 0; c <= 2; c++) {
+      *f ^= e[3] + 9;
+      e = __builtin_shufflevector(
+          ~__builtin_shufflevector(bla, e, 1, 4, 3, 4), e, 0, 1, 1, 7);
+    }
+  return g;
+}
+
+int main() {
+  int j = d ();
+  if (b != 0)
+    __builtin_abort ();
+}