ia64.c (TARGET_VECTOR_MODE_SUPPORTED_P): New.

        * config/ia64/ia64.c (TARGET_VECTOR_MODE_SUPPORTED_P): New.
        (ia64_const_ok_for_letter_p): New.
        (ia64_const_double_ok_for_letter_p): New.
        (ia64_extra_constraint): New.
        (ia64_expand_vecint_compare): New.
        (ia64_expand_vcondu_v2si): New.
        (ia64_expand_vecint_cmov): New.
        (ia64_expand_vecint_minmax): New.
        (ia64_print_operand): Add 'v'.
        (ia64_preferred_reload_class): New.
        (ia64_vector_mode_supported_p): New.
        * config/ia64/ia64.h (UNITS_PER_SIMD_WORD): New.
        (PREFERRED_RELOAD_CLASS): Move to function.
        (CONST_OK_FOR_LETTER_P): Move to function.
        (CONST_DOUBLE_OK_FOR_LETTER_P): Move to function.
        (CONSTRAINT_OK_FOR_Q, CONSTRAINT_OK_FOR_R): Remove.
        (CONSTRAINT_OK_FOR_S, CONSTRAINT_OK_FOR_T): Remove.
        (EXTRA_CONSTRAINT): Move to function.
        * config/ia64/ia64.md: Include vect.md.
        (itanium_class): Add mmalua.
        (type): Handle it.
        * config/ia64/itanium1.md (1_mmalua): New.  Add it to bypasses.
        (1b_mmalua): New.
        * config/ia64/itanium2.md (2_mmalua, 2b_mmalua): Similarly.
        * config/ia64/predicates.md (gr_reg_or_0_operand): Accept any
        CONST0_RTX.
        (const_int_2bit_operand): New.
        (fr_reg_or_0_operand): New.
        * config/ia64/ia64-modes.def: Add vector modes.
        * config/ia64/ia64-protos.h: Update.
        * config/ia64/vect.md: New file.

        * gcc.dg/vect/vect.exp: Enable for ia64.
        * lib/target-supports.exp (check_effective_target_vect_int): Likewise.
        (check_effective_target_vect_float): Likewise.
        (check_effective_target_vect_no_align): Likewise.
        * gcc.dg/vect/vect-30.c: XFAIL for vect_no_align.
        * gcc.dg/vect/vect-8.c: Likewise.

From-SVN: r92862

5 files changed, 24 insertions, 5 deletions

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 8c4ea6a..56e4aed 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,4 +1,14 @@
+2005-01-03  Richard Henderson  <rth@redhat.com>
+
+	* gcc.dg/vect/vect.exp: Enable for ia64.
+	* lib/target-supports.exp (check_effective_target_vect_int): Likewise.
+	(check_effective_target_vect_float): Likewise.
+	(check_effective_target_vect_no_align): Likewise.
+	* gcc.dg/vect/vect-30.c: XFAIL for vect_no_align.
+	* gcc.dg/vect/vect-8.c: Likewise.
+
 2005-01-03  Uros Bizjak <uros@kss-loka.si>
+
 	PR target/19235
 	* gcc.dg/pr19236-1.c: New test case.
 
diff --git a/gcc/testsuite/gcc.dg/vect/vect-30.c b/gcc/testsuite/gcc.dg/vect/vect-30.c
index 056d689..c6f03ed 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-30.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-30.c
@@ -59,4 +59,6 @@ int main (void)
   return 0;
 }
 
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect"  } } */
+/* Need misalignment support, or cgraph to delay emitting the arrays until
+   after vectorization can force-align them.  */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail vect_no_align } } } */
diff --git a/gcc/testsuite/gcc.dg/vect/vect-8.c b/gcc/testsuite/gcc.dg/vect/vect-8.c
index 960eb34..7712a02 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-8.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-8.c
@@ -34,4 +34,6 @@ int main (void)
   return main1 (N);
 }
 
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  } } */
+/* Need misalignment support, or cgraph to delay emitting the arrays until
+   after vectorization can force-align them.  */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail vect_no_align } } } */
diff --git a/gcc/testsuite/gcc.dg/vect/vect.exp b/gcc/testsuite/gcc.dg/vect/vect.exp
index 14e4597..94fd56c 100644
--- a/gcc/testsuite/gcc.dg/vect/vect.exp
+++ b/gcc/testsuite/gcc.dg/vect/vect.exp
@@ -65,6 +65,8 @@ if [istarget "powerpc*-*-*"] {
     } else {
 	set dg-do-what-default compile
     }
+} elseif [istarget "ia64-*-*"] {
+    set dg-do-what-default run
 } else {
     return
 }
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 19d95af..defb4d4 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -455,7 +455,8 @@ proc check_effective_target_vect_int { } {
 	      || [istarget powerpc*-*-*]
 	      || [istarget x86_64-*-*]
 	      || [istarget sparc*-*-*]
-	      || [istarget alpha*-*-*] } {
+	      || [istarget alpha*-*-*]
+	      || [istarget ia64-*-*] } {
 	   set et_vect_int_saved 1
 	}
     }
@@ -496,7 +497,8 @@ proc check_effective_target_vect_float { } {
 	if { [istarget i?86-*-*]
 	      || [istarget powerpc*-*-*]
 	      || [istarget mipsisa64*-*-*]
-	      || [istarget x86_64-*-*] } {
+	      || [istarget x86_64-*-*]
+	      || [istarget ia64-*-*] } {
 	   set et_vect_float_saved 1
 	}
     }
@@ -583,7 +585,8 @@ proc check_effective_target_vect_no_align { } {
     } else {
 	set et_vect_no_align_saved 0
 	if { [istarget mipsisa64*-*-*]
-	     || [istarget sparc*-*-*] } {
+	     || [istarget sparc*-*-*]
+	     || [istarget ia64-*-*] } {
 	    set et_vect_no_align_saved 1
 	}
     }