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author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2014-04-23 15:29:06 +0000 |
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committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2014-04-23 15:29:06 +0000 |
commit | ea1e916837085fa51565e55a57c8c2f9dfaab9ce (patch) | |
tree | f864363ded52df8e4d3eafe37f06272f91ea456a /gcc/testsuite | |
parent | f7d5cf8df3193f8f6e62501def08e4b0b1baadbc (diff) | |
download | gcc-ea1e916837085fa51565e55a57c8c2f9dfaab9ce.zip gcc-ea1e916837085fa51565e55a57c8c2f9dfaab9ce.tar.gz gcc-ea1e916837085fa51565e55a57c8c2f9dfaab9ce.tar.bz2 |
[ARM][3/3] Recognise bitwise operations leading to SImode rev16
* config/arm/arm.md (arm_rev16si2): New pattern.
(arm_rev16si2_alt): Likewise.
* config/arm/arm.c (arm_new_rtx_costs): Handle rev16 case.
* gcc.target/arm/rev16.c: New test.
From-SVN: r209705
Diffstat (limited to 'gcc/testsuite')
-rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/arm/rev16.c | 35 |
2 files changed, 39 insertions, 0 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 9f1e7ce..f25a2b7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2014-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + * gcc.target/arm/rev16.c: New test. + +2014-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + * gcc.target/aarch64/rev16_1.c: New test. 2014-04-23 Richard Biener <rguenther@suse.de> diff --git a/gcc/testsuite/gcc.target/arm/rev16.c b/gcc/testsuite/gcc.target/arm/rev16.c new file mode 100644 index 0000000..1c869b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/rev16.c @@ -0,0 +1,35 @@ +/* { dg-options "-O2" } */ +/* { dg-do run } */ + +extern void abort (void); + +typedef unsigned int __u32; + +__u32 +__rev16_32_alt (__u32 x) +{ + return (((__u32)(x) & (__u32)0xff00ff00UL) >> 8) + | (((__u32)(x) & (__u32)0x00ff00ffUL) << 8); +} + +__u32 +__rev16_32 (__u32 x) +{ + return (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) + | (((__u32)(x) & (__u32)0xff00ff00UL) >> 8); +} + +int +main (void) +{ + volatile __u32 in32 = 0x12345678; + volatile __u32 expected32 = 0x34127856; + + if (__rev16_32 (in32) != expected32) + abort (); + + if (__rev16_32_alt (in32) != expected32) + abort (); + + return 0; +} |