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author | Thomas Preud'homme <thomas.preudhomme@arm.com> | 2016-10-27 10:19:27 +0000 |
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committer | Thomas Preud'homme <thopre01@gcc.gnu.org> | 2016-10-27 10:19:27 +0000 |
commit | ddb92ab95f6ba681423ba55db9910821735544c1 (patch) | |
tree | dc19465bb22dad76890b8479bf1e991d20871f24 /gcc/testsuite | |
parent | 33cab74617734fdda5b39bd645d13361cd92af23 (diff) | |
download | gcc-ddb92ab95f6ba681423ba55db9910821735544c1.zip gcc-ddb92ab95f6ba681423ba55db9910821735544c1.tar.gz gcc-ddb92ab95f6ba681423ba55db9910821735544c1.tar.bz2 |
Enable ARMv8-M atomic and synchronization support for ARMv8-M Baseline
2016-10-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config/arm/arm.h (TARGET_HAVE_LDREX): Define for ARMv8-M Baseline.
(TARGET_HAVE_LDREXBH): Likewise.
(TARGET_HAVE_LDACQ): Likewise.
gcc/testsuite/
* gcc.target/arm/atomic-comp-swap-release-acquire-3.c: New test.
* gcc.target/arm/atomic-op-acq_rel-3.c: Likewise.
* gcc.target/arm/atomic-op-acquire-3.c: Likewise.
* gcc.target/arm/atomic-op-char-3.c: Likewise.
* gcc.target/arm/atomic-op-consume-3.c: Likewise.
* gcc.target/arm/atomic-op-int-3.c: Likewise.
* gcc.target/arm/atomic-op-relaxed-3.c: Likewise.
* gcc.target/arm/atomic-op-release-3.c: Likewise.
* gcc.target/arm/atomic-op-seq_cst-3.c: Likewise.
* gcc.target/arm/atomic-op-short-3.c: Likewise.
From-SVN: r241615
Diffstat (limited to 'gcc/testsuite')
-rw-r--r-- | gcc/testsuite/ChangeLog | 13 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-3.c | 10 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-3.c | 10 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/arm/atomic-op-acquire-3.c | 10 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/arm/atomic-op-char-3.c | 10 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/arm/atomic-op-consume-3.c | 11 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/arm/atomic-op-int-3.c | 10 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/arm/atomic-op-relaxed-3.c | 10 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/arm/atomic-op-release-3.c | 10 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-3.c | 10 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/arm/atomic-op-short-3.c | 10 |
11 files changed, 114 insertions, 0 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 512e9a6..9e37729 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,16 @@ +2016-10-27 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * gcc.target/arm/atomic-comp-swap-release-acquire-3.c: New test. + * gcc.target/arm/atomic-op-acq_rel-3.c: Likewise. + * gcc.target/arm/atomic-op-acquire-3.c: Likewise. + * gcc.target/arm/atomic-op-char-3.c: Likewise. + * gcc.target/arm/atomic-op-consume-3.c: Likewise. + * gcc.target/arm/atomic-op-int-3.c: Likewise. + * gcc.target/arm/atomic-op-relaxed-3.c: Likewise. + * gcc.target/arm/atomic-op-release-3.c: Likewise. + * gcc.target/arm/atomic-op-seq_cst-3.c: Likewise. + * gcc.target/arm/atomic-op-short-3.c: Likewise. + 2016-10-27 Bin Cheng <bin.cheng@arm.com> * gcc.dg/fold-convmaxconv-1.c: New test. diff --git a/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-3.c b/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-3.c new file mode 100644 index 0000000..0191f7a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2 -fno-ipa-icf" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-comp-swap-release-acquire.x" + +/* { dg-final { scan-assembler-times "ldaex" 4 } } */ +/* { dg-final { scan-assembler-times "stlex" 4 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-3.c new file mode 100644 index 0000000..f2ed32d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-acq_rel.x" + +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-acquire-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-acquire-3.c new file mode 100644 index 0000000..bba1c27 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-acquire-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-acquire.x" + +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-char-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-char-3.c new file mode 100644 index 0000000..17117ee --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-char-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-char.x" + +/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-consume-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-consume-3.c new file mode 100644 index 0000000..8352f0c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-consume-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-consume.x" + +/* Scan for ldaex is a PR59448 consume workaround. */ +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-int-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-int-3.c new file mode 100644 index 0000000..d4f1db3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-int-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-int.x" + +/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-relaxed-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-relaxed-3.c new file mode 100644 index 0000000..09b5ea9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-relaxed-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-relaxed.x" + +/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-release-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-release-3.c new file mode 100644 index 0000000..2b136f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-release-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-release.x" + +/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-3.c new file mode 100644 index 0000000..7f38d42 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-seq_cst.x" + +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-short-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-short-3.c new file mode 100644 index 0000000..60ae42eb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-short-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-short.x" + +/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ |